XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 28

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel as shown in
programming. These registers support 8,
data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in
the UART channel register is paired along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately. Furthermore, the XR17V352 supports
PCI burst mode for read/write operation of up to 256 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
The XR17V352 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/
written to, as shown in
support burst transactions:
For example, the locations for channel 1 are:
The RX FIFO data (up to the maximum 256 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0) and 0x500 (channel 1). This operation is
at least 16 times faster than reading the data in 256 separate 8-bit memory reads of RHR register (0x000 for
channel 0 and 0x400 for channel 1).
2.0 TRANSMIT AND RECEIVE DATA
2.1
2.1.1
WITH N
Read n+0 to n+3
Read n+4 to n+7
R
EAD
FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT
Channel N: (for channels 0 through 1) where M = 4N + 1.
Channel 1:
Etc.
RX FIFO,
O
Normal Rx FIFO Data Unloading at locations 0x100 and 0x500
E
RRORS
RX FIFO
TX FIFO
RX FIFO + status
RX FIFO
TX FIFO
RX FIFO + status
Table
FIFO Data n+3
FIFO Data n+7
B
4. The following is an extract from the table showing the memory locations that
YTE
3
:
:
:
:
:
:
16,
24 and 32 bits wide format. In the 32-bit format, it increases the
FIFO Data n+2
FIFO Data n+6
0xM00 - 0xMFF (256 bytes)
0xM00 - 0xMFF (256 bytes)
0x(M+1)0 - 0x(M+2)FF (256 bytes data + 256 bytes status)
0x0500 - 0x05FF (256 bytes)
0x0500 - 0x05FF (256 bytes)
0x0600 - 0x07FF (256 bytes data + 256 bytes status)
B
YTE
28
2
FIFO Data n+1
FIFO Data n+5
B
YTE
1
Table 4
FIFO Data n+0
FIFO Data n+4
B
YTE
set to ease
REV. 1.0.1
0