XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 31

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
There are 2 UARTs channel [1:0] in the V352. Each has its own 256-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit [7] sets the prescaler to
divide the internal 125MHz clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling.
The BRG divisor (DLL, DLM and DLD registers) defaults to 1 (DLL = 0x01, DLM = 0x00, DLD = 0x00). The
DLL and DLM registers provide the integer part of the divisor and the DLD register provides the fractional part
of the divisor. Only the four lower bits of the DLD are implemented and they are used to select a value from 0
(for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator Registers DLL,
DLM and DLD provides the capability for selecting the operating data rate.
standard and non-standard data rates when using the internal 125MHz clock at 16X clock rate. If the pre-scaler
is used (MCR bit [7] = 1), the output data rate will be 4 times less than that shown in
rate, these data rates would double. At 4X sampling rate, these data rates would quadruple. Also, when using
8X or 4X sampling mode, note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is an odd number.
For data rates not listed in
The closest divisor that is obtainable in the V352 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
3.0 UART
3.1
Required Divisor (decimal) = (125MHz clock frequency / prescaler) / (serial data rate x 16),
Required Divisor (decimal) = (125MHz clock frequency / prescaler / (serial data rate x 8),
Required Divisor (decimal) = (125MHz clock frequency / prescaler / (serial data rate x 4),
ROUND( (Required Divisor - TRUNC (Required Divisor) )*16)/16 + TRUNC (Required Divisor), where
WITH
WITH
WITH
Programmable Baud Rate Generator with Fractional Divisor
8XMODE =0
8XMODE = 1
8XMODE = 0
DLD = ROUND ( (Required Divisor-TRUNC(Required Divisor) )*16)
AND
AND
AND
Table
4XMODE = 0
4XMODE = 0
4XMODE = 1
DLL = TRUNC (Required Divisor) & 0xFF
11, the divisor value can be calculated with the following equation(s):
DLM = TRUNC( Required Divisor) >> 8
31
HIGH PERFORMANCE DUAL PCI EXPRESS UART
16
- 0.0625) in increments of 0.0625 (1/16) to
Table 11
shows the divisor for some
Table
11. At 8X sampling
XR17V352