ATTINY5-MAH Atmel, ATTINY5-MAH Datasheet - Page 35

• Manufacturer Part Number: ATTINY5-MAH
• Description: IC MCU AVR 512B FLASH 8UDFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY5-MAH

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Peripherals: POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 512B (256 x 16)
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UFDFN Exposed Pad
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

8.4.3
8127D–AVR–02/10
RSTFLR – Reset Flag Register
• Bits 2:0 – VLM2:0: Trigger Level of Voltage Level Monitor
These bits set the trigger level for the voltage level monitor, as described in
Table 8-4.
For VLM voltage levels, see Figures 17-42, 17-43, 17-44, and 17-45.
The Reset Flag Register provides information on which reset source caused an MCU Reset.
• Bits 7:4, 2– Res: Reserved Bits
These bits are reserved bits in ATtiny4/5/9/10 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
Bit
0x3B
Read/Write
Initial Value
VLM2:0
000
001
010
011
100
101
110
111
Setting the Trigger Level of Voltage Level Monitor.
R
7
–
0
VLM1H
VLM1L
Label
VLM0
VLM2
VLM3
R
6
–
0
R
5
–
0
Description
Voltage Level Monitor disabled
Triggering generates a regular Power-On Reset (POR).
The VLM flag is not set
Triggering sets the VLM Flag (VLMF) and generates a VLM
interrupt, if enabled
R
4
–
0
WDRF
R/W
X
3
Not allowed
R
2
–
0
EXTRF
R/W
X
1
ATtiny4/5/9/10
PORF
R/W
X
0
Table 8-4
RSTFLR
below.
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