AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 170
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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22.6.4.1
22.6.4.2
170
SAM7SE512/256/32 Preliminary
Standard Wait States
External Wait States
Each chip select can be programmed to insert one or more wait states during an access on the
corresponding memory area. This is done by setting the WSEN field in the corresponding
SMC_CSR
grammed in the NWS field in the same register.
Below is the correspondence between the number of standard wait states programmed and the
number of clock cycles during which the NWE pulse is held low:
For each additional wait state programmed, an additional cycle is added.
Figure 22-13. One Standard Wait State Access
Notes:
The NWAIT input pin is used to insert wait states beyond the maximum standard wait states pro-
grammable or in addition to. If NWAIT is asserted low, then the SMC adds a wait state and no
changes are made to the output signals, the internal counters or the state. When NWAIT is de-
asserted, the SMC completes the access sequence.
WARNING: Asserting NWAIT low stops the core’s clock and thus stops program execution.
The input of the NWAIT signal is an asynchronous input. To avoid any metastability problems,
NWAIT is synchronized before using it. This operation results in a two-cycle delay.
NWS must be programmed as a function of synchronization time and delay between NWAIT fall-
ing and control signals falling (NRD/NWE), otherwise SMC will not function correctly.
Note:
WARNING: If NWAIT is asserted during a setup or hold timing, the SMC does not function
correctly.
0 wait states
1 wait state
NWS
1. Early Read Protocol
2. Standard Read Protocol
Where external NWAIT synchronization is equal to 2 cycles.
The minimum value for NWS if NWAIT is used, is 3.
(“SMC Chip Select Registers” on page
≥
Wait Delay from nrd/nwe
A[22:0]
NWE
MCK
NRD
NCS
(1)
1 Wait State Access
(2)
+
external_nwait Synchronization Delay
1/2 clock cycle
1 clock cycle
196). The number of cycles to insert is pro-
6222F–ATARM–14-Jan-11
+
1
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