AT91SAM7SE256B-AUR Atmel, AT91SAM7SE256B-AUR Datasheet - Page 208
AT91SAM7SE256B-AUR
Manufacturer Part Number
AT91SAM7SE256B-AUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-AUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
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23.6.5
23.6.5.1
Figure 23-7. Self-refresh Mode Behavior
208
SDRAMC_SRR
SDCKE
A[12:0]
SDWE
SDCK
SDCS
Write
RAS
CAS
SAM7SE512/256/32 Preliminary
Power Management
Self-refresh Mode
SRCB = 1
Self-refresh mode is used in power-down mode, i.e., when no access to the SDRAM device is
possible. In this case, power consumption is very low. The mode is activated by programming
the self-refresh command bit (SRCB) in SDRAMC_SRR. In self-refresh mode, the SDRAM
device retains data without external clocking and provides its own internal clocking, thus per-
forming its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care”
except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM
Controller provides a sequence of commands and exits self-refresh mode, so the self-refresh
command bit is disabled.
To re-activate this mode, the self-refresh command bit must be re-programmed.
The SDRAM device must remain in self-refresh mode for a minimum period of t
remain in self-refresh mode for an indefinite period. This is described in
Self Refresh Mode
to the SDRAM Controller
Access Request
T
Figure 23-7
XSR
= 3
6222F–ATARM–14-Jan-11
RAS
below.
Row
and may
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