MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 11

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Note that this example calculation is for a point-to-point connection. If more than 1 memory device is
connected to the bus, the rise / fall time will be slower and the trace length may be longer.
Control signals like CS, ADDRESS, RAS, CAS, and WE are not critical and can be routed without these
constraints.
5.4
5.5
The i.MX28 processor EMI pin locations have been optimized to facilitate single layer DRAM signal
routing. The layout example below shows an ideal fan-out between the i.MX28 processor and a DDR2
memory device where nearly all the routing is accomplished on a signal layer. The routing can be achieved
with low cost PCB manufacturing using 5 mils trace/space and 8/16 through-hole vias. Note that this
layout shows fan-out only, differential pair routing is not complete, and does not include length matching.
Freescale Semiconductor
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In terminated systems, “daisy chain” routing is recommended because the impedance can be
matched along the whole trace. In non-terminated systems, Y routing is much better because it
makes the trace lengths shorter, which reduces the capacitive loading.
For 2 external DRAM components, pin swapping the data signals within a byte lane can be
performed to improve/optimize routing. This is particularly useful when the one DRAM is placed
on the top side of the board and the other is placed on the bottom side.
Routing to Multiple DRAM Devices
Layout Examples
i.MX28 Layout and Design Guidelines, Rev. 0
DRAM Memory
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