MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 8

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

DRAM Memory
5.2
The guidelines below mainly focus on DDR2 routing (including low voltage,1.5V, DDR2). However, most
of the these guidelines also apply to mDDR.
Summary of key signal groups:
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Vias can be strategically placed to create channels for the supply bypass capacitors to be placed
underneath the i.MX28 processor and close to the EMI supply pins as shown below:
Address/Command (Ax, BAx, RAS#, CAS#, WE#)
— Single ended, parallel, terminated to VTT, registered on rising edge of clock.
Control (CS#, CKE, ODT)
— Single ended, parallel, terminated to VTT, registered on rising edge of clock.
— Each bank has its own control signal (less loading).
Clocks (CLK, CLK#)
— Differential, terminated on die with ODT.
Data mask (DQMx)
— Single ended input, terminated on die with ODT.
— One data mask for each byte lane.
Routing
i.MX28 Layout and Design Guidelines, Rev. 0
Freescale Semiconductor