MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 14

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Ethernet
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8.1
8.2
In RMII mode, the i.MX28 processor supplies the 50MHz ethernet clock signal to the ethernet PHY. This
signal must be routed very carefully due to its high speed. Poor layout of this signal can cause ethernet
PHY clocking issues. To prevent any issues, follow these guidelines:
8.3
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Ethernet
If the magnetic is a discrete component, then it should be placed no greater than 1 inch away from
the ethernet jack.
The distance between the ethernet PHY and the magnetics should be 25mm (1 in.) or greater. The
1 in. design rule is considered good design practice among PHY vendors to isolate the PHY from
the magnetics.
Keep the PHY device and the differential TX/RX pairs at least 1 inch from the edge of the PCB,
up to the magnetics. For an integrated magnetics ethernet jack, the differential pairs should be
routed to the back of the integrated jack, away from the board edge.
The 49.9 ohm pull-up resistors on RX/TX should be placed within 400 mils of the ethernet PHY
and should be placed next to the RX/TX pairs to minimize stubs. This also ensures similar RX/TX
transmit paths.
Minimize trace length. This will help to minimize trace capacitance, which can slow the edge rates
of the ethernet clock. It will also minimize the chances of picking up noise from other source on
the PCB such as high speed digital traces or current switching power planes/traces.
Route the clock in isolation away from other traces and noise sources.
Must be routed over a continuous ground plane. It should not be routed across any plane splits or
traces on adjacent layers.
Must be routed with 100 ohm differential impedance and 50 ohm single ended impedance.
Must be routed over a solid ground plane to maintain a controlled impedance over the entire trace
route.
Trace lengths for each pair should be matched.
Use a minimum distance of 30 mils between TX and RX pairs.
Component Placement
Ethernet Clock
Ethernet TX and RX pairs between the ethernet PHY and the
magnetics
i.MX28 Layout and Design Guidelines, Rev. 0
Freescale Semiconductor