AD6620AS Analog Devices Inc, AD6620AS Datasheet - Page 34

• Manufacturer Part Number: AD6620AS
• Description: IC DGTL RCVR SIGNAL PROC 80-PQFP
• Manufacturer: Analog Devices Inc

Specifications of AD6620AS

• Rohs Status: RoHS non-compliant
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 80-MQFP, 80-PQFP
• Mounting Type: *
• Applications: -

AD6620
Mode = 1
If the MODE input is held high the interface is in Mode 1. In
Mode 1 the RD signal becomes the data strobe (DS) and the
WR signal becomes a read/write (R/W) select signal. In this
DTACK
DTACK
D[7:0]
A[2:0]
D[7:0]
A[2:0]
CLK
R/W
DS
CS
CLK
R/W
DS
CS
2
3
2
3
2
NOTES:
1
2
3
1
2
1
DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),
CLK "N=2" OTHERWISE.
THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS
AND FORCE DTACK HIGH.
t
SAM
NOTES:
1
2
3
THE NEXT WRITE MAY BE INITIATED ON CLK, N
ON RISING EDGE OF "N+3" CLK, DTACK IS DRIVEN LOW.
THESE SIGNALS (R/W AND DS) MAY REMAIN IN LOW STATE TO CONTINUE WRITING DATA.
CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+3 SHOWN) TO COMPLETE WRITE
AND FORCE DTACK HIGH.
t
t
t
SC
t
SAM
SAM
ZR
N
t
SC
N
N+1
ADDRESS VALID
DATA VALID
ADDRESS VALID
N+1
t
N+2
mode the DTACK signal goes low when data is available during
a read or when data has been latched during a write. The DTACK
signal stays low until the DS signal is released.
DD
t
DTACK
N+2
t
DTACK
t
t
t
HC
HM
HA
DATA VALID
N+3
t
t
HC
SC
t
t
N+3
t
HC
DTACK
SC
t
ZD
N+4
t
t
HC
HA
t
DTACK
N
N