AD6620AS Analog Devices Inc, AD6620AS Datasheet - Page 36

• Manufacturer Part Number: AD6620AS
• Description: IC DGTL RCVR SIGNAL PROC 80-PQFP
• Manufacturer: Analog Devices Inc

Specifications of AD6620AS

• Rohs Status: RoHS non-compliant
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 80-MQFP, 80-PQFP
• Mounting Type: *
• Applications: -

AD6620
Example of Serial Port W/R Operation
The example shown below demonstrates writing and reading
from the AD6620. For this example, the chip is set up in diver-
sity channel real mode. Therefore, there four data words (two Is
and two Qs) are generated as receiver data. Thus four commands
can be shifted into the SDI port. These are shown below. Addi-
tionally, the chip is configured with a word length of 16 bits.
The AD6620 response with five words per frame (two Is, two
Qs and the appended read word).
The table above shows the serial output bits for this configura-
tion. As the I and Q data are being shifted out, the SDI pin is
telling the chip what data to return during the appended data
field. During the A-I portion of the frame, the hex word 4703 is
shifted into the chip. Breaking this word down, the command
instructs the AD6620 to write an ‘03’ into the AMR register.
The next word, 4600, writes a ‘00’ into the LAR. Therefore, the
chip is so configured that the next command will either read
from or write to internal memory space ‘300’ hex, the Mode
Control Register. The next word on the SDI pin is 80XX. This
indicates a read from DR0. Note that the second half of the read
word is ignored. During the B-Q word, another read or write
can be set up. In this case, 4603 changes the internal memory to
point to ‘303,’ the NCO frequency, thus setting up subsequent
access of this register. Now during the append data frame, the
AD6620 sends any read words that are pending due to read
requests. In this case, the contents of register ‘300.’ Since the
chip is in single channel complex mode and running, the chip
responds with ‘0AXX.’ ‘0A’ indicates that the chip is in diver-
sity channel real mode and running as a Sync master. The ‘XX’
is indeterminate and would have been the results of a second
read if one had been requested.
PAR/SER
The Serial Port shares pins with a Parallel Output Port. These
pins are arbitrated by the PAR/SER pin. In order to operate the
chip with the Parallel Output Data Port PAR/SER must be high
while RESET is brought high. For Serial Port operation, PAR/
SER must be held low while RESET is brought high. PAR/SER
should remain valid while the AD6620 is processing (should
only be changed in RESET). PAR/SER should be hardwired on
a given design.
SBM
Serial Bus Master. When SBM is high, the AD6620 generates
SCLK and SDFS. When SBM is low, the AD6620 accepts
external SCLK and SDFS signals. When configured as a bus
master the SCLK signal can be used to strobe data into the DSP
interface. When used with another AD6620 in Serial Cascade
Mode, SCLK can be taken from the master AD6620 and used
to shift data out from the cascaded device. In this situation SDFS
of the Cascaded AD6620 is connected to the SDFE pin of the
master AD6620. When an AD6620 is in Serial Cascade Mode,
all of the serial port activities are controlled by the external
signals SCLK and SDFS.
Regardless of whether the chip is a Serial Bus Master or is in
Serial Cascade Mode, the AD6620 Serial Port functions are
identical except for the source of the SCLK and SDFS pins.
SDO
SDI
A-I
XXXX
4703
Table XVI. SDI Data Format
A-Q
XXXX
4600
B-I
XXXX
80XX
B-Q
XXXX
4603
Append
0AXX
XXXX
SCLK
SCLK is an output when SBM is high; SCLK is an input when
SBM is low. In either case the SDI input is sampled on the
falling edge of SCLK, and all outputs are switched on the rising
edge of SCLK. The SDFS pin is sampled on the falling edge of
SCLK. This allows the AD6620 to recognize the SDFS in time
to initiate a frame on the very next SCLK rising edge. The maxi-
mum speed of this port is 33.5 MHz or half of the master CLK
signal, whichever is lower. Care should be taken with this signal.
Even when the AD6620 is selected as a serial bus master, reflec-
tions on this line will cause the output shifters to ‘double shift’
output data causing corrupt serial data. If this signal is going to
a back plane of more than several inches, the line should either
be buffered or be matched to the impedance of the back plane.
See the Applications section of this data sheet for information
on driving the transmission lines.
SDI
Serial Data Input. Serial Data is sampled on the falling edge of
SCLK. This pin is used to write the internal control registers of
the AD6620 or to write the address of an internal location to be
read. These activities are described later in the Serial Frame
Structure section. If this pin is not used to write data into the
control port it should be tied low.
SDO
Serial Data Output. Serial output data is switched on the rising
edge of SCLK. On the very next SCLK cycle after an SDFS,
the MSB of A channel: I data is shifted. On every subsequent
SCLK edge a new piece of data is shifted out on the SDO pin
until the last bit of data is shifted out. The last bit of data
shifted is A channel: Q data in either of the Single Channel
Modes or the B channel: Q data in the Diversity Channel Real
Data. SDO is three-stated when the serial port is outside its
time-slot. This allows the AD6620 to share the SDI of a DSP,
with other AD6620s. In order to ensure that the three-state
condition of this pin does not cause a problem there should
either be a bus holder on this signal or there should be a weak
pull-down resistor placed on it. This will ensure that the SDO
pin is always in a valid logic state.
SDFS
SDFS is the Serial Data Frame Sync signal. SDFS is an output
when SBM is high; SDFS is an input when SBM is low. SDFS
is sampled on the falling edge of SCLK. When SDFS is sampled
high, the AD6620 serial port will become active on the next
rising edge of SCLK for a complete serial time-slot. When SBM
is high SDFS will pulse high for one SCLK cycle before an
active serial time-slot is to be initiated and a transfer will begin
immediately on the next rising edge of SCLK. When used as a
serial slave, the SDFS pin must not receive more than one SDFS
per frame. As with SCLK, care should be taken with this signal.
Even when the AD6620 is selected as a serial bus master, reflec-
tions on this line can cause erratic framing results. If this signal
is going to a back plane of more than several inches, the line
should either be buffered or be matched to the impedance of the
back plane. See the applications section of this data sheet for
information on driving the transmission lines.
SDFE
Serial Data Frame End output. SDFE will go high during the
last SCLK cycle of an active time-slot. The SDFE output of a
master AD6620 can be tied to the input SDFS of an AD6620 in
Serial Cascade Mode in order to provide a hardwired time-slot
scenario. When the Last Bit of SDO data is shifted out of the