WM8985GEFL Wolfson Microelectronics, WM8985GEFL Datasheet - Page 39

Audio CODECs Multimedia CODEC with Class D HP

WM8985GEFL

Manufacturer Part Number
WM8985GEFL
Description
Audio CODECs Multimedia CODEC with Class D HP
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8985GEFL

Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-32
Minimum Operating Temperature
- 25 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM8985GEFL/R
Manufacturer:
TAIYO
Quantity:
4 023
Part Number:
WM8985GEFL/R
Manufacturer:
WOLFSON
Quantity:
20 000
Production Data
w
Table 14 ADC Control
SELECTABLE HIGH PASS FILTER
Table 15 ADC Enable Control
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit.
ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
A selectable high pass filter is provided and enabled as default. To disable this filter set HPFEN=0.
The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order,
with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a
cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are
shown in Table 16.
R14 (0Eh)
ADC Control
R14 (0Eh)
ADC Control
REGISTER
ADDRESS
REGISTER
ADDRESS
6:4
7
8
BIT
0
1
3
BIT
ADCLPOL
ADCRPOL
ADCOSR128
HPFCUT
HPFAPP
HPFEN
LABEL
LABEL
The oversampling rate of the ADC can be adjusted using the
000
0
1
DEFAULT
0
0
0
DEFAULT
Application mode cut-off frequency
See Table 16 for details.
PLL Output Clock Division Ratio
00 = divide by 1
01 = divide by 2
10 = divide by 3
11 = divide by 4
Note: HPCUT and OPCLKDIV cannot be
set independently
Select audio mode or application mode
0 = Audio mode (1
1 = Application mode (2
HPFCUT)
High Pass Filter Enable
0 = disabled
1 = enabled
ADC left channel polarity adjust:
0 = normal
1 = inverted
ADC right channel polarity adjust:
0 = normal
1 = inverted
0 = 64x (lower power)
1 = 128x (best performance)
ADC oversample rate select:
DESCRIPTION
DESCRIPTION
st
PD, Rev 4.6, July 2009
order, fc = ~3.7Hz)
nd
order, fc =
WM8985
39

Related parts for WM8985GEFL