CS8427-CZZ Cirrus Logic Inc, CS8427-CZZ Datasheet - Page 42

• Manufacturer Part Number: CS8427-CZZ
• Description: Audio DSPs 96 kHz Digital Audio Transceiver
• Manufacturer: Cirrus Logic Inc

Specifications of CS8427-CZZ

• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6.3 mA to 76.6 mA
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Input Voltage: 4.8 V to 5.8 V
• Package / Case: TSSOP-28
• Rohs Compliant: Yes
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: TSSOP
• No. Of Pins: 28
• Supply Voltage Max: 5.5V
• Supply Voltage Min: 4.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. HARDWARE MODE DESCRIPTION
Hardware mode is selected by connecting the H/S
pin to ‘1’. Hardware Mode data flow is shown in
Figure
ceiver, and routed to the serial audio output port.
Different audio data synchronous to RMCK may be
input into the serial audio input port, and output
through the AES3 transmitter.
The channel status data, user data and validity bit
information are handled in 2 alternative modes: A
and B, determined by a start-up resistor on the
COPY pin. In mode A, the received PRO, COPY,
ORIG, EMPH, and AUDIO channel status bits are
output on pins. The transmitted channel status bits
are copied from the received channel status data,
and the transmitted U and V bits are 0.
In mode B, only the COPY and ORIG pins are out-
put, and reflect the received channel status data.
The transmitted channel status bits, user data and
validity bits are input serially through the PRO/C,
EMPH/U and AUDIO/V pins.
shows the timing requirements.
42
19. Audio data is input through the AES3 re-
RXP
RXN
RMCK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
AES3 Rx
&
Decoder
RERR
Figure 13 on page 22
VL+
H/S
Figure 19. Hardware Mode
PRO/C
SDOUT
OSCLK
Serial
Audio
Output
COPY ORIG EMPH/U AUDIO/V TCBL
The APMS pin allows the serial audio input port to
be set to master or slave.
If a validity, parity, bi-phase or lock receiver error
occurs, the current audio sample is passed un-
modified to the serial audio output port.
Start-up options are shown in
and allow choice of the serial audio output port as
a master or slave, whether TCBL is an input or an
output, the audio serial ports formats and the
source of the transmitted C, U and V data.
13.1
In hardware mode, only a limited number of alter-
native serial audio port formats are available.
These formats are described by
page 43
equivalent software mode bit settings for each for-
mat. Timing diagrams are shown in
page 23
OLRCK
C & U bit Data Buffer
Serial Audio Port Formats
ILRCK
and
and
ISCLK
Serial
Audio
Input
Table 4 on page
Figure 16 on page
SDIN
AES3
Encoder
& Tx
Table 2 on page
43, which define the
24.
APMS
TXP
TXN
Figure 15 on
CS8427
Table 3 on
DS477F5
43,