CS8427-CZZ Cirrus Logic Inc, CS8427-CZZ Datasheet - Page 45

• Manufacturer Part Number: CS8427-CZZ
• Description: Audio DSPs 96 kHz Digital Audio Transceiver
• Manufacturer: Cirrus Logic Inc

Specifications of CS8427-CZZ

• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6.3 mA to 76.6 mA
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Input Voltage: 4.8 V to 5.8 V
• Package / Case: TSSOP-28
• Rohs Compliant: Yes
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: TSSOP
• No. Of Pins: 28
• Supply Voltage Max: 5.5V
• Supply Voltage Min: 4.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS477F5
ILRCK
ISCLK
SDIN
TCBL
OSCLK
OLRCK
SDOUT
AUDIO/V
PRO/C
APMS
VL+
VL2+
H/S
TXP
TXN
ORIG
12
13
14
15
16
17
18
19
20
21
23
27
24
25
26
28
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on
the SDIN pin.
Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Data Port (Input) - Audio data serial input pin.
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is
high during the first sub-frame of a transmitted channel status block, and low at all other times.
When operated as input, driving TCBL high for at least three OMCK clocks will cause the next
transmitted sub-frame to be the start of a channel status block.
Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT
pin
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on
the SDOUT pin. Frequency will be the output sample rate (Fs)
Serial Audio Output Data (Output) - Audio data serial output pin
Audio Channel Status Bit / V-Bit (Input/Output) - Reflects either the state of the audio/non-
audio Channel Status bit in the incoming AES3 data stream or is the Validity bit data input for
the AES3 transmitted data stream, clocked by OLRCK.
PRO Channel Status Bit / C-Bit (Input/Output) - Reflects either the state of the Profes-
sional/Consumer Channel Status bit in the incoming AES3 data stream or is the serial C-bit
input for the AES3 transmitted data, clocked by OLRCK.
Serial Audio Input Port Master/Slave Select (Input) - APMS should be connected to VL+ to
set serial audio input port as a master, or connected to DGND to set the port as a slave.
Positive Digital Power (Input) - Typically +3.3 V or +5.0 V.
Hardware/Software Mode Control (Input) - Determines the method of controlling the opera-
tion of the CS8427, and the method of accessing CS and U data. In software mode, device
control and CS and U data access is primarily through the control port, using a microcontroller.
Hardware mode provides an alternate mode of operation and access to the CS and U data
through dedicated pins. This pin should be permanently tied to VL+ or DGND
Differential Line Driver (Output) - Drivers transmit AES3 data and are pulled low while the
CS8427 is in the reset state.
ORIG Channel Status Bit (Output) - SCMS generation indicator. This is decoded from the
incoming category code and the L bit. A low output indicates that the source of the audio data
stream is a copy. A high indicates that the source of the audio data stream is an original
recording. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
CS8427
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