PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 94

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
5.5.2
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
TABLE 5-2:
DS30491C-page 92
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
Name
x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
EEPGD
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
CFGS
CMIP
CMIE
CMIF
Bit 6
—
bit 21
Bit 5
—
—
—
—
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
FREE
INTE
EEIP
EEIF
EEIE
Bit 4
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
TMR0IF
WREN
LVDIP
LVDIE
LVDIF
5.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
5.6
See Section 24.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
Bit 2
TMR3IP
TMR3IF
TMR3IE
Flash Program Operation During
Code Protection
INTF
Bit 1
WR
PROTECTION AGAINST SPURIOUS
WRITES
CCP2IP
CCP2IF
CCP2IE
RBIF
Bit 0
RD
 2004 Microchip Technology Inc.
--00 0000
0000 0000
0000 0000
0000 0000
0000 0000
xx-0 x000
-1-1 1111
-0-0 0000
-0-0 0000
POR, BOR
Value on:
—
--00 0000
0000 0000
0000 0000
0000 0000
0000 0000
uu-0 u000
-1-1 1111
-0-0 0000
-0-0 0000
Value on
all other
Resets
—