PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 311

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 23-45: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER
REGISTER 23-46: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0
 2004 Microchip Technology Inc.
RXFCON0
RXFCON1
bit 7-0
bit 7-5
bit 4-0
bit 7
Unimplemented: Read as ‘0’
FLC4:FLC0: Filter Length Count bits
Mode 0:
Not used; forced to ‘00000’.
Mode 1, 2:
00000-10010 = 0
If DLC3:DLC0 = 0000 No bits will be compared with incoming data bits
If DLC3:DLC0 = 0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will
If DLC3:DLC0 = 0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0,
If DLC3:DLC0 = 0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0,
Legend:
R = Readable bit
- n = Value at POR
bit 7
RXFnEN: Receive Filter n Enable bit
0 = Filter is disabled
1 = Filter is enabled
Legend:
R = Readable bit
- n = Value at POR
RXF15EN
Note 1: This register is available in Mode 1 and 2 only.
RXF7EN
Note 1: This register is available in Mode 1 and 2 only.
R/W-0
R/W-0
U-0
—
RXF14EN RXF13EN RXF12EN RXF11EN RXF10EN RXF9EN
RXF6EN
R/W-0
R/W-0
U-0
—
PIC18F6585/8585/6680/8680
18 bits are available for standard data byte filter. Actual number of bits
used depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> if
configured as RX buffer) of message being received.
be compared with the corresponding number of data bits of the
incoming message
will be compared with the corresponding number of data bits of the
incoming message
will be compared with the corresponding number of data bits of the
incoming message
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
RXF5EN
R/W-1
R/W-0
U-0
—
RXF4EN
R/W-0
FLC4
R/W-1
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RXF3EN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
FLC3
R/W-1
R/W-0
RXF2EN
R/W-0
R/W-1
R/W-0
FLC2
n
x = Bit is unknown
x = Bit is unknown
1]
RXF1EN
R/W-0
R/W-1
R/W-0
FLC1
(1)
DS30491C-page 309
(1)
RXF0EN
RXF8EN
R/W-0
R/W-1
R/W-0
FLC0
bit 0
bit 0