PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 387

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
Q1
Q1
PC
CNT
If CNT
If CNT
Q1
PC
PC
=
=
=
=
=
register ‘f’
operation
operation
operation
Decrement f, skip if 0
[ label ] DECFSZ f [,d [,a]]
0
d
a
(f) – 1
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
No
No
No
0010
Q2
Q2
Q2
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+2)
f
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
11da
operation
operation
operation
GOTO
DECFSZ
Process
Data
No
No
No
Q3
Q3
Q3
ffff
CNT, 1, 1
LOOP
destination
operation
operation
operation
Write to
PIC18F6585/8585/6680/8680
No
No
No
Q4
Q4
Q4
ffff
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Decrement f, skip if not 0
[ label ] DCFSNZ
0
d
a
(f) – 1
skip if result
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
=
=
=
=
=
f
[0,1]
[0,1]
255
by a 2-word instruction.
?
TEMP - 1,
0;
Address (ZERO)
0;
Address (NZERO)
dest,
DCFSNZ
:
:
11da
operation
operation
operation
Process
Data
0
No
No
No
Q3
Q3
Q3
DS30491C-page 385
ffff
TEMP, 1, 0
f [,d [,a]]
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff