PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 163

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low-power oscillator rated up to 200 kHz. It will
continue to run during Sleep. It is primarily intended for
a 32 kHz crystal. Table 12-1 shows the capacitor
selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
TABLE 12-1:
12.3
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to 0FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 interrupt enable bit, TMR1IE
(PIE1<0>).
TABLE 12-2:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TMR1L
TMR1H
T1CON
Legend:
32.768 kHz Epson C-001R32.768K-A
Osc Type
Name
Note 1: Microchip suggests 33 pF as a starting
LP
2: Higher capacitance increases the stability
3: Since each resonator/crystal has its own
4: Capacitor values are for design guidance
Timer1 Oscillator
Timer1 Interrupt
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
GIE/GIEH PEIE/GIEL
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
PSPIF
PSPIE
PSPIP
point in validating the oscillator circuit.
of the oscillator but also increases the
start-up time.
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
components.
only.
RD16
Bit 7
Crystal to be Tested:
32 kHz
Freq
CAPACITOR SELECTION
FOR THE ALTERNATE
OSCILLATOR
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
ADIE
ADIP
ADIF
Bit 6
—
values
TBD
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
C1
TMR0IE
RCIE
RCIP
RCIF
Bit 5
(1)
of
INT0IE
TBD
20 PPM
Bit 4
TXIF
TXIE
TXIP
PIC18F6585/8585/6680/8680
external
C2
(1)
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
12.4
If the CCP module is configured in Compare mode
to
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L register
pair effectively becomes the period register for Timer1.
12.5
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is valid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
Note:
Bit 2
generate
Resetting Timer1 Using a CCP
Trigger Output
Timer1 16-Bit Read/Write Mode
TMR2IF
TMR2IE
TMR2IP
INT0IF
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Bit 1
a
TMR1IE
TMR1IP
TMR1IF
Bit 0
RBIF
“special
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0111 1111 0111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on
DS30491C-page 161
event
Value on
all other
Resets
trigger”