PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 104

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
REGISTER 7-1:
DS30491C-page 102
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER (ADDRESS FA6h)
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access Flash program or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: Flash Program/Data EE Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed
0 = The write operation completed
WREN: Flash Program/Data EE Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
bit 7
EEPGD
Note:
R/W-x
(cleared by completion of erase operation)
programming in normal operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
R/W-x
CFGS
U = Unimplemented bit, read as ‘0’
S = Settable bit
‘0’ = Bit is cleared
U-0
—
R/W-0
FREE
WRERR
R/W-x
WREN
R/W-0
 2004 Microchip Technology Inc.
- n = Value after erase
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0