LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 87
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.)
Pin Number
105*
100
101
102
103
104
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Pin Function
VCCIO4
VCCIO4
VCCIO3
VCCIO3
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB25B
PB33A
GND4
GND3
GND4
GND3
CFG2
CFG1
Bank
LFECP6/LFEC6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
DOUT/CSON
BUSY/SISPI
DI/CSSPIN
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
D7/SPID0
VREF1_4
VREF2_4
VREF2_3
VREF1_3
RDQS24
WRITEN
BDQS22
CS1N
CSN
4-21
Pin Function
VCCIO4
VCCIO4
VCCIO3
VCCIO3
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
PB33B
PB41A
PR36B
PR36A
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
GND4
GND3
GND4
GND3
CFG2
CFG1
LatticeECP/EC Family Data Sheet
LFECP10/LFEC10
Bank
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Pinout Information
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
DOUT/CSON
BUSY/SISPI
DI/CSSPIN
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
D7/SPID0
VREF1_4
VREF2_4
VREF2_3
VREF1_3
WRITEN
BDQS30
RDQS33
CS1N
CSN
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