LFEC3E-5TN144C Lattice, LFEC3E-5TN144C Datasheet - Page 98
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LFEC3E-5TN144C
Manufacturer Part Number
LFEC3E-5TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs Pb-Free
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-5TN144C
Number Of Logic Blocks
384
Number Of Macrocells
3100
Number Of Programmable I/os
97
Data Ram Size
56320
Delay Time
5 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
3100
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA
Number
GND
GND
GND
GND
GND
GND
Ball
M2
M1
N1
N2
M4
M3
R1
N3
N4
N5
R4
R3
R5
R6
N6
M6
K2
K1
P1
P2
P3
P4
P5
P6
T2
T3
T4
T5
T6
T7
P7
L3
L5
L4
L2
L1
-
Ball Function
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PL29A
PL29B
PL30A
PL30B
PL31A
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
PL35B
PL36A
PL36B
GND6
GND6
GND5
GND5
GND5
GND5
VCCJ
TMS
TDO
-
Bank
LFECP10/LFEC10
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
LLM0_PLLC_FB_A
LLM0_PLLT_FB_A
LLM0_PLLC_IN_A
LLM0_PLLT_IN_A
Dual Function
VREF1_6
VREF2_6
BDQS14
LDQS33
4-32
Ball Function
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PL37A
PL37B
PL38A
PL38B
PL39A
PL39B
PL40A
PL40B
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
PL44B
GND6
GND6
GND6
GND5
GND5
GND5
GND5
VCCJ
TMS
TDO
LatticeECP/EC Family Data Sheet
Bank
LFECP15/LFEC15
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
LVDS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Pinout Information
LLM0_PLLC_FB_A
LLM0_PLLT_FB_A
LLM0_PLLC_IN_A
LLM0_PLLT_IN_A
Dual Function
VREF1_6
VREF2_6
LDQS41
BDQS14
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