LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 129

• Manufacturer Part Number: LFXP2-5E-5FTN256I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5FTN256I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 172
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 172
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 9-3. Dynamic Phase and Duty Cycle Adjust Ports
WRDEL (Write Delay)
The fine delay option supports SPI4.2. The PLL has a coarse phase adjust feature in which a cycle is divided into
16 equal steps (22.5°). For SPI4.2 running at 840 Mbps, the clock frequency is 420 MHz. At this frequency, the
period is roughly 150 ps. This is slightly too coarse for dynamic phase adjust requirements. It may be more effective
to use increments half as large. Combined with coarse phase adjust, a 70 ps (nominal) step provides effectively 32
steps of phase adjustment. This fine delay only applies to CLKOS (just like the coarse phase adjust). This is conve-
nient since it allows one GPLL to be used for both read and write (where read uses CLKOS and write uses
CLKOP).
PLL Attributes
The PLL utilizes several attributes that allow the configuration of the PLL through source constraints and a prefer-
ence file. The following section details these attributes and their usage.
FIN
The input frequency can be any value within the specified frequency range based on the divider settings.
CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV
These dividers determine the output frequencies of each output clock. The user is not allowed to input an invalid
combination. Valid combinations are determined by the input frequency, the dividers, and the PLL specifications.
Note: Unlike PLLs in the LatticeECP™, LatticeEC™, LatticeXP™ and MachXO™ devices, the CLKOP divider val-
ues are the same whether or not CLKOS is used.
The CLKOP_DIV value is calculated to maximize the f
CLKOP_FREQ in conjunction with the CLKI_DIV and CLKFB_DIV values. These value settings are designed such
that the output clock duty cycle is as close to 50% as possible. Table 9-4 shows the possible divider ranges.
Table 9-4. Divider Ranges
FREQUENCY_PIN_CLKI, FREQUENCY_PIN_CLKOP, FREQUENCY_PIN_CLKOK
These input and output clock frequencies determine the divider values.
CLKOP Frequency Tolerance
When the desired output frequency is not achievable, users may enter the frequency tolerance of the clock output.
PHASEADJ (Phase Shift Adjust)
The PHASEADJ attribute is used to select Phase Shift for CLKOS output. The phase adjustment is programmable
in 22.5° increments.
CLKI Divider Setting
CLKFB Divider Setting
CLKOP Divider Setting
CLKOK Divider Setting
Attribute
DPHASE[3:0]
DDUTY[3:0]
Port Name
CLKOP_DIV
CLKOK_DIV
CLKFB_DIV
CLKI_DIV
Name
I/O
I
I
9-7
Dynamic Phase Adjust inputs
Dynamic Duty Cycle Adjust inputs
VCO
2, 4, 8, 16, 32, 48, 64, 80
within the specified range based on FIN and
2, 4, 6,.., 126, 128
Description
1 to 43
1 to 43
Value
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
Default
1
1
8
2