LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 22
LFXP2-5E-5FTN256I
Manufacturer Part Number
LFXP2-5E-5FTN256I
Description
FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5FTN256I
Number Of Macrocells
5000
Number Of Programmable I/os
172
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
172
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 2-5. Clock Divider Connections
Clock Distribution Network
LatticeXP2 devices have eight quadrant-based primary clocks and between six and eight flexible region-based sec-
ondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to sup-
port high speed interfaces. The clock inputs are selected from external I/Os, the sysCLOCK PLLs, or routing. Clock
inputs are fed throughout the chip via the primary, secondary and edge clock networks.
Primary Clock Sources
LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs
and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There
are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources.
CLKOP (GPLL)
ECLK
RELEASE
RST
2-8
CLKDIV
LatticeXP2 Family Data Sheet
÷1
÷2
÷4
÷8
Architecture
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