LFXP2-5E-5FTN256I Lattice, LFXP2-5E-5FTN256I Datasheet - Page 273
LFXP2-5E-5FTN256I
Manufacturer Part Number
LFXP2-5E-5FTN256I
Description
FPGA - Field Programmable Gate Array 5K LUTs 172 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5FTN256I
Number Of Macrocells
5000
Number Of Programmable I/os
172
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
172
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 13-13. Simulink Design
Targeting the sysDSP Block by Instantiating Primitives
The sysDSP Block can be targeted by instantiating the sysDSP Block primitives into the design. The advantage of
instantiating primitives is that it provides access to all ports and sets all available parameters. The disadvantage of
this flow is that all this customization requires extra coding by the user. Appendix A details the syntax for the sys-
DSP Block primitives.
sysDSP Block Control Signal and Data Signal Descriptions
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
RST
SIGNEDA
SIGNEDB
ACCUMSLOAD
ADDNSUB
SOURCEA
SOURCEB
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
www.latticesemi.com
Asynchronous reset of selected registers
Dynamic signal: 0 = unsigned, 1 = signed
Dynamic signal: 0 = unsigned, 1 = signed
Dynamic signal: 0 = accumulate, 1 = load
Dynamic signal: 0 = subtract, 1 = add
Dynamic signal: 0 = parallel input, 1 = shift input
Dynamic signal: 0 = parallel input, 1 = shift input
13-14
Lattice XP2 sysDSP Usage Guide
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