LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 38

• Manufacturer Part Number: LFSC3GA25E-7FN900C
• Description: FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFSC3GA25E-7FN900C

• Number Of Macrocells: 25000
• Number Of Programmable I/os: 132 to 942
• Data Ram Size: 1916928
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 0.95 V
• Package / Case: FPBGA-900
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
VDDAX25 needs to be connected independent of the use of the SERDES. This supply is used to control the
SERDES CML I/O regardless of the SERDES being used in the design.
Supported Source Synchronous Interfaces
The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify
the implementation of Source Synchronous interfaces. Table 2-11 lists Source Synchronous and DDR/QDR stan-
dards supported in the LatticeSC. For additional detail refer to technical information at the end of the data sheet.
Table 2-11. Source Synchronous Standards Table
flexiPCS™ (Physical Coding Sublayer Block)
flexiPCS Functionality
The LatticeSC family combines a high-performance FPGA fabric, high-performance I/Os and large embedded
RAM in a single industry leading architecture. LatticeSC devices also feature up to 32 channels of embedded
SERDES with associated Physical Coding Sublayer (PCS) logic. The flexiPCS logic can be configured to support
numerous industry standard high-speed data transfer protocols.
Each channel of flexiPCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial
data transfers at data rates up to 3.8 Gbps. The PCS logic in each channel can be configured to support an array of
popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or
above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X specification), 1.02 or 2.04 Gbps Fibre Channel,
PCI-Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a num-
ber of configurations to allow users flexibility in designing their own high-speed data interface.
Protocols requiring data rates above 3.8 Gbps can be accommodated by dedicating either one pair or all four chan-
nels in one flexiPCS quad block to one data link. One quad can support full-duplex serial data transfers at data
rates up to 15.2 Gbps. A single flexiPCS quad can be configured to support 10Gb Ethernet (with a fully compliant
XAUI interface), 10Gb Fibre Channel, and x4 PCI-Express and 4x RapidIO.
The flexiPCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the
FPGA logic which can also be geared to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Each
SERDES pin can be DC coupled independently and can allow for both high-speed and low-speed operation down
to DC rates on the same SERDES pin, as required by some Serial Digital Video applications.
The ispLEVER design tools from Lattice support all modes of the flexiPCS. Most modes are dedicated to applica-
tions associated with a specific industry standard data protocol. Other more general purpose modes allow a user to
define their own operation. With ispLEVER, the user can define the mode for each quad in a design. Nine modes
are currently supported by the ispLEVER design flow:
RapidIO
SPI4.2 (POS-PHY4)/NPSI
SFI4/XSBI
XGMII
CSIX
QDRII/QDRII+ memory interface
DDR memory interface
DDRII memory interface
RLDRAM memory interface
1. Memory width is dependent on the system design and limited by the number of I/Os in the device.
Source Synchronous Standard
Clocking
DDR
DDR
DDR
SDR
DDR
SDR
DDR
DDR
DDR
DDR
1
2-34
Speeds (MHz)
156.25
500
500
334
667
250
300
240
333
400
LatticeSC/M Family Data Sheet
Data Rate (Mbps)
1000
1000
667
312
250
600
480
667
800
Architecture