LFSC3GA25E-7FN900C Lattice, LFSC3GA25E-7FN900C Datasheet - Page 50

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LFSC3GA25E-7FN900C

Manufacturer Part Number
LFSC3GA25E-7FN900C
Description
FPGA - Field Programmable Gate Array 25.4K LUTs 378 3G SERDES 1.2V -7 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFSC3GA25E-7FN900C

Number Of Macrocells
25000
Number Of Programmable I/os
132 to 942
Data Ram Size
1916928
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
0.95 V
Package / Case
FPBGA-900
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFSC3GA25E-7FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Z
R
V
V
V
V
V
V
T
T
T
Note: Data is for 6mA differential current drive. Other differential driver current options are available.
Lattice Semiconductor
PURESPEED I/O Differential Electrical Characteristics
LVDS
Mini-LVDS
V
V
V
I
V
V
V
V
V
V
I
T
Notes:
1. Data is for 3.5mA differential current drive. Other differential driver current options are available.
2. If the low power mode of the input buffer is used, the minimum V
Parameter Symbol
IN
SAB
O
R
ODUTY
IDUTY
OD
OS
THD
CM
Parameter
T
OH
OL
OD
OS
R
INP,
THD
CM
OD
, T
ID
Symbol
OD
OS
, T
F
V
F
INM
Input voltage
Differential input threshold (Q-Q)
Input common mode voltage
Input current
Output high voltage for V
Output low voltage for V
Output voltage differential
Change in V
low
Output voltage offset
Change in V
Output short circuit current
Output rise and fall times, 20% to
80%
Parameter Description
Single-ended PCB trace impedance
Differential termination resistance
Output voltage, differential, |V
Output voltage, common mode, |V
Change in V
Change in V
Input voltage, differential, |V
Input voltage, common mode, |V
Output rise and fall times, 20% to 80%
Output clock duty cycle
Input clock duty cycle
OD
OS
between H and L
between high and
OD
OS
Over Recommended Operating Conditions
Over Recommended Operating Conditions
, between H and L
, between H and L
OP
OP
Description
or V
or V
OM
OM
INP
Power on or power off
R
R
(V
(V
V
shorted
OP
OD
T
T
OP
OP
- V
= 100 Ohm
= 100 Ohm
INP
- V
= 0V Driver outputs
OP
- V
- V
INM
OM
Test Conditions
+ V
OM
OM
+ V
CM
|
|
3-6
INM
), R
)/2, R
is 600 mV.
OM
|/2 0.3+(V
|/2
T
= 100 Ohm
T
= 100 Ohm
Min.
300
200
30
60
45
40
1
THD
DC and Switching Characteristics
/2)
LatticeSC/M Family Data Sheet
+/-100
1.125
Min.
0.9V
0.05
250
0
Typ.
100
1.2
50
Typ.
1.38
1.03
1.20
350
500
1.2
2.1-(V
Max.
150
600
600
500
1.4
75
55
60
50
50
THD
1.375
+/-10
Max.
2.35
1.60
450
2.4
50
50
12
ps
/2)
T
Units
ohms
ohms
R
Units
mV
mV
mV
mV
ps
, T
%
%
V
mV
mV
mV
mV
mA
µA
V
V
V
V
V
F

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