SI5364-H-BL Silicon Laboratories Inc, SI5364-H-BL Datasheet - Page 11

• Manufacturer Part Number: SI5364-H-BL
• Description: IC CLK MULT SONET/SDH 99-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5364-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(V
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 01, 10 (255/238, 238/255 Scal-
ing)
Jitter Transfer Bandwidth (see Figure 9)
Wander/Jitter Transfer Peaking
Wander/Jitter at 6400 Hz Bandwidth
(BWSEL[1:0] = 11)
Jitter Tolerance (see Figure 8)
CLKOUT RMS Jitter Generation
FEC[1:0] = 00 (1/1 Scaling)
CLKOUT RMS Jitter Generation
FEC[1:0] = 01, 10 (255/238, 238/255 scal-
ing)
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 00 (1/1 Scaling)
CLKOUT Peak-Peak Jitter Generation
FEC[1:0] = 01, 10 (255/238, 238/255 scal-
ing)
Jitter Transfer Bandwidth (see Figure 9)
Wander/Jitter Transfer Peaking
Acquisition Time
Clock Output Wander with
Temperature Gradient
Initial Frequency Accuracy in Digital Hold
Mode (first 100 ms with supply voltage and
temperature held constant)
Clock Output Frequency Accuracy Over
Temperature in Digital Hold Mode
Clock Output Frequency Accuracy Over
Supply Voltage in Digital Hold Mode
Clock Output Phase Step
Notes:
DD33
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
= 3.3 V ± 5%, TA = –20 to 85 °C)
of nanoseconds per millisecond. The equivalent ps/ μ s unit is used here since the maximum phase transient magnitude
for the Si5364 (t
Parameter
PT_MTIE
1,2
) never reaches one nanosecond.
J
J
J
J
J
C
Symbol
J
t
GEN(RMS)
GEN(RMS)
C
C
PT_MTIE
GEN(PP)
GEN(PP)
GEN(PP)
C
TOL(PP)
DH_V33
CO_TG
F
F
DH_FA
T
DH_T
J
J
BW
BW
AQ
P
P
Rev. 2.5
clock input and VALTIME = 0
CAL_ACTV low, with valid
Constant Supply Voltage
During Clock Switching
Selected until entering
Constant Temperature
Gradient < 10 °C/min;
Stable Input Clock;
RSTN/CAL high to
Stable Input Clock
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
12 kHz to 20 MHz
50 kHz to 80 MHz
800 Hz Loop BW
Test Condition
BW = 3200 Hz
BW = 6400 Hz
Temperature
f = 6400 Hz
Digital Hold
< 3200 Hz
f = 640 Hz
< 6400 Hz
f = 64 Hz
1/1
1000
–200
Min
100
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3200
6400
1.03
0.38
1.01
0.45
0.05
16.2
Typ
195
7.9
4.6
0.0
9.3
2.8
7.1
3.0
25
—
—
—
—
—
0
Si5364
Max Unit
10.0
0.05
12.0
12.0
350
500
200
5.0
1.4
0.5
1.4
0.6
5.5
5.5
7.0
40
30
—
—
—
—
—
.1
ppm
ppm
ppm
min
°C/
/°C
ms
ps/
Hz
dB
Hz
dB
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
/V
11