SI5364-H-BL Silicon Laboratories Inc, SI5364-H-BL Datasheet - Page 32

• Manufacturer Part Number: SI5364-H-BL
• Description: IC CLK MULT SONET/SDH 99-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5364-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5364
32
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
Pin #
C3
C4
low state if the input is not driven from an external source.
DECDELAY
INCDELAY
Pin Name
Table 10. Pin Descriptions (Continued)
I/O
I*
I*
Signal Level
LVTTL
LVTTL
Rev. 2.5
Increment Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the INCDELAY pin adds a fixed delay
to the Si5364’s clock outputs. The fixed delay time is
equal to twice the period of the 622 MHz output clock
(t
output clock (f
the input clock. The frequency of the 622 MHz output
clock (fo_622) is scaled additionally according to the
setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note: INCDELAY is ignored when the Si5364 is operating
Decrement Output Phase Delay.
The INCDELAY and DECDELAY pins can adjust the
phase of the Si5364 clock outputs. Adjustment is
accomplished by driving a pulse (a transition from
low to high and then back to low) into one of the pins
while the other pin is held at a logic low level.
Each pulse on the DECDELAY pin removes a fixed
delay from the Si5364’s clock outputs. The fixed
delay time is equal to twice the period of the 622
MHz output clock (t
of the 622 MHz output clock (f
the frequency of the input clock. The frequency of the
622 MHz output clock (fo_622) is scaled additionally
according to the setting of the FEC[1:0] pins.
When the phase of the Si5364 clock outputs is
adjusted using the INCDELAY and/or DECDELAY
pins, the output clock moves to its new phase setting
at a rate of change that is determined by the setting
of the BWSEL[1:0] pins.
Note: INCDELAY is ignored when the Si5364 is operating
DELAY
in digital hold (DH) mode.
in digital hold (DH) mode.
= 2/f
o_622
o_622
). The frequency of the 622 MHz
) is nominally 32x the frequency of
DELAY
Description
= 2/f
o_622
o_622
) is nominally 32x
). The frequency