SI5364-H-BL Silicon Laboratories Inc, SI5364-H-BL Datasheet - Page 28

• Manufacturer Part Number: SI5364-H-BL
• Description: IC CLK MULT SONET/SDH 99-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5364-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5364
28
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
Pin #
A10
C10
A9
K2
low state if the input is not driven from an external source.
RSTN/CAL
DH_ACTV
Pin Name
F_ACTV
RVRT
Table 10. Pin Descriptions (Continued)
I/O
O
O
I*
I*
Signal Level
LVTTL
LVTTL
LVTTL
LVTTL
Rev. 2.5
REF/CLKIN_F is Active.
Active high output indicates that REF/CLKIN_F is
selected as the clock input to the DSPLL.
The DH_ACTV output takes precedence over this
signal as an indicator of the DSPLL clock input sta-
tus. When this output is high and the DH_ACTV out-
put is low, REF/CLKIN_F is being used by the
DSPLL to generate the SONET/SDH compatible out-
put clocks. When this output is high and the
DH_ACTV output is high, REF/CLKIN_F is selected,
but the DSPLL is in digital hold mode. Refer to
DH_ACTV.
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the current
state of the DSPLL and forces the DSPLL to
continue generation of the output clocks with no
additional phase or frequency information from the
input clocks.
Revertive Switching.
Selects the revertive switching mode during auto-
matic switching operation. If this input is high during
automatic switching, the revertive switching mode is
selected. The highest priority reference source that is
valid is selected as the DSPLL reference source.
See AUTOSEL pin description. During manual mode
of operation, this input has no effect.
Reset/Calibrate.
When low, the internal circuitry enters the reset mode
and all LVTTL outputs are forced into a high-imped-
ance state. Also, the CLKOUT_n+ and CLKOUT_n–
pins are forced to a nominal CML logic LOW and
HIGH respectively. The FRQSEL_n[1:0] setting must
be set to 01, 10, or 11 to enable this mode. This
mode is useful for in-circuit test applications.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition, enables the device
outputs, and initiates self-calibration of the DSPLL.
At the completion of self-calibration, the DSPLL
begins to lock to the selected clock input signal.
Description