SI5364-H-BL Silicon Laboratories Inc, SI5364-H-BL Datasheet - Page 21

• Manufacturer Part Number: SI5364-H-BL
• Description: IC CLK MULT SONET/SDH 99-PBGA
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5364-H-BL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

and are also used for connection of the external
compensation circuit.
The compensation circuit for the internal voltage
regulator consists of a resistor and a capacitor in series
between the V
capacitor is selected with an appropriate equivalent
series resistance (ESR), the discrete series resistor can
be eliminated. The target RC time constant for this
combination is 15 to 50 µs. The capacitor used in the
Si5364 evaluation board is a 33 µF tantalum capacitor
with an ESR of 0.8 Ω . This gives an RC time constant of
26.4 µs and no discrete resistor is required. (See
Figure 7 on page 14.) The Venkel part number,
TA6R3TCR336KBR, is an example of a capacitor that
meets these specifications.
To get optimal performance from the Si5364 device, the
power supply noise spectrum must comply with the plot
in Figure 13. This plot shows the power supply noise
tolerance mask for the Si5364. The customer should
provide a 3.3 V supply that does not have noise density
in excess of the amount shown in the diagram.
V
230
n
4.5
(μV/√Hz)
DD25
node and ground. In practice, if a
10 kHz
Figure 13. Power Supply Noise Tolerance Mask
500 kHz
Rev. 2.5
However, the diagram cannot be used as spur criteria
for a power supply that contains single tone noise.
2.13. Design and Layout Guidelines
Precision clock circuits are susceptible to board noise
and EMI. To take precautions against unacceptable
levels of board noise and EMI affecting performance of
the Si5364, consider the following:
Excessive high-frequency harmonics of the input clock
should be minimized. The use of filters on the input
clock signal can be used to remove high-frequency
harmonics.
Use an isolated, local plane to connect the V
pins. Avoid running signal traces over or below this
plane without a ground plane in between.
Route all I/O traces between ground planes as much
as possible
Maintain an input clock amplitude in the 200 mV
500 mV
PP
differential range.
100 Mhz
Si5364
f
DD25
PP
to
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