PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 194

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
TABLE 11-9:
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39977C-page 194
RE5/CANTX
RE6/RX2/DT2
RE7/TX2/CK2
Legend:
Note 1:
PORTE
LATE
TRISE
PADCFG1
ANCON0
Legend: Shaded cells are not used by PORTE.
Note 1:
Pin Name
Name
2:
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Unavailable for 40 and 44-pin devices (PIC18F4XK0).
Alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration
bit is cleared.
Unimplemented on 44-pin devices, read as ‘ 0 ’.
ANSEL7
TRISE7
RE7
LATE7
RDPU
CANTX
Bit 7
PORTE FUNCTIONS (CONTINUED)
Function
RE5
RE6
RX2
RE7
CK2
DT2
TX2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1,2)
ANSEL6
Setting
TRISE6
RE6
LATE6
REPU
TRIS
Bit 6
0
1
0
0
1
1
1
1
0
1
0
0
1
(1)
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
ANSEL5
RFPU
TRISE5
LATE5
RE5
Bit 5
I/O Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
(1)
ST
ST
ST
ST
ST
ST
(1)
Preliminary
LATE<5> data output.
PORTE<5> data input.
CAN bus TX.
LATE<6> data output.
PORTE<6> data input.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial data input (EUSART module); user must configure
as an input.
LATE<7> data output.
PORTE<7> data input.
Asynchronous serial data output (EUSART module); takes priority over
port data.
Synchronous serial clock output (EUSART module); user must
configure as an input.
Synchronous serial clock input (EUSART module); user must configure
as an input.
RGPU
ANSEL4
TRISE4
RE4
LATE4
Bit 4
(1)
(1)
ANSEL3
Bit 3
RE3
—
—
—
ANSEL2
TRISE2
Description
LATE2
Bit 2
RE2
—
 2011 Microchip Technology Inc.
ANSEL1
TRISE1
LATE1
Bit 1
RE1
—
CTMUDS
ANSEL0
TRISE0
LATE0
Bit 0
RE0