PIC18F45K80-I/PT Microchip Technology, PIC18F45K80-I/PT Datasheet - Page 622

• Manufacturer Part Number: PIC18F45K80-I/PT
• Description: MCU PIC 32KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K80-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F45K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
DS39977C-page 622
Half-Bridge PWM Output .................................. 280, 287
High-Voltage Detect Operation
HLVD Characteristics................................................ 575
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation (VDIRMAG = 0)........ 392
MSSP Clock Synchronization ................................... 318
MSSP I
MSSP I
Parallel Slave Port (PSP) Read ................................ 200
Parallel Slave Port (PSP) Write ................................ 199
PWM Auto-Shutdown with Auto-Restart
PWM Auto-Shutdown with Firmware Restart............ 286
PWM Direction Change ............................................ 283
PWM Direction Change at Near 100%
PWM Output ............................................................. 268
Repeated Start Condition.......................................... 327
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................. 356
Slave Synchronization .............................................. 299
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) .......................................... 298
SPI Mode (Slave Mode, CKE = 0) ............................ 300
SPI Mode (Slave Mode, CKE = 1) ............................ 300
Steering Event at Beginning of Instruction
Steering Event at End of Instruction
Synchronous Reception (Master Mode, SREN) ....... 359
Synchronous Transmission....................................... 357
Synchronous Transmission (Through TXEN) ........... 358
Time-out Sequence on POR w/ PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock ........................... 576
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence ..................................... 331
C Bus Data ............................................................. 583
C Bus Start/Stop Bits.............................................. 582
C Master Mode (7 or 10-Bit Transmission) ............ 329
C Master Mode (7-Bit Reception) ........................... 330
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) ........... 315
C Slave Mode (10-Bit Reception, SEN = 1) ........... 320
C Slave Mode (10-Bit Transmission)...................... 316
C Slave Mode (7-bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............. 311
C Slave Mode (7-Bit Reception, SEN = 1) ............. 319
C Slave Mode (7-Bit Transmission)........................ 313
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ......... 331
(VDIRMAG = 1)................................................. 393
ADMSK = 01001) .............................................. 314
ADMSK = 01011) .............................................. 312
Sequence (7 or 10-Bit Addressing Mode)......... 321
Enabled............................................................. 286
Duty Cycle......................................................... 284
Timer (OST) and Power-up Timer (PWRT) ...... 573
Rise > T
(STRSYNC = 1) ................................................ 290
(STRSYNC = 0) ................................................ 290
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
2
2
C Bus Data .................................................. 584
C Bus Start/Stop Bits .................................. 584
PWRT
)..................................................... 87
DD
, V
DD
DD
DD
), Case 1 ........................ 87
), Case 2 ........................ 87
Rise T
DD
DD
).............................. 88
, V
PWRT
DD
) ............... 86
Preliminary
Timing Diagrams and Specifications
Top-of-Stack Access......................................................... 107
TSTFSZ ............................................................................ 527
Two-Speed Start-up.................................................. 461, 480
Two-Word Instructions
TXSTAx Register
Timer1 Gate Count Enable Mode ............................. 223
Timer1 Gate Single Pulse Mode............................... 225
Timer1 Gate Single Pulse/Toggle
Timer1 Gate Toggle Mode........................................ 224
Timer3 Gate Count Enable Mode ............................. 234
Timer3 Gate Single Pulse Mode............................... 236
Timer3 Gate Single Pulse/Toggle
Timer3 Gate Toggle Mode........................................ 235
Transition for Entry to Idle Mode................................. 73
Transition for Entry to SEC_RUN Mode ..................... 69
Transition for Entry to Sleep Mode ............................. 72
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ................ 73
Transition for Wake from Sleep (HSPLL) ................... 72
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ...................................... 71
Capture/Compare/PWM Requirements .................... 577
CLKO and I/O Requirements............................ 572, 573
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements ................................... 570
HLVD Characteristics ............................................... 575
I
I
Internal RC Accuracy (INTOSC)............................... 571
MSSP I
MSSP I
PLL Clock ................................................................. 571
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
IESO (CONFIG1H, Internal/External
Example Cases......................................................... 111
BRGH Bit .................................................................. 343
2
2
C Bus Data Requirements (Slave Mode) ............... 583
C Bus Start/Stop Bits Requirements
Combined Mode ............................................... 226
Combined Mode ............................................... 237
(INTOSC to HSPLL) ......................................... 480
PRI_RUN Mode.................................................. 71
PRI_RUN Mode (HSPLL) ................................... 69
Requirements ................................................... 586
Requirements ................................................... 586
(Master Mode, CKE = 0)................................... 578
(Master Mode, CKE = 1)................................... 579
(Slave Mode, CKE = 0)..................................... 580
(CKE = 1).......................................................... 581
(Slave Mode) .................................................... 582
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 574
Requirements ................................................... 576
Oscillator Switchover Bit................................... 464
2
2
C Bus Data Requirements .......................... 585
C Bus Start/Stop Bits Requirements........... 584
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