74AUP1G09GW,125 NXP Semiconductors, 74AUP1G09GW,125 Datasheet - Page 2

IC GATE AND LP 2INPUT TSSOP5

74AUP1G09GW,125

Manufacturer Part Number
74AUP1G09GW,125
Description
IC GATE AND LP 2INPUT TSSOP5
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74AUP1G09GW,125

Product
AND
Number Of Gates
1
Propagation Delay Time
4.9 ns, 5.9 ns, 6.5 ns
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-5
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5391-2
NXP Semiconductors
3. Ordering information
Table 1.
4. Marking
Table 2.
[1]
5. Functional diagram
74AUP1G09
Product data sheet
Type number
74AUP1G09GW
74AUP1G09GM
74AUP1G09GF
74AUP1G09GN
74AUP1G09GS
Type number
74AUP1G09GW
74AUP1G09GM
74AUP1G09GF
74AUP1G09GN
74AUP1G09GS
Fig 1.
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Logic symbol
B
A
Ordering information
Marking
1
2
Package
Temperature range Name
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
001aad598
4
Y
All information provided in this document is subject to legal disclaimers.
Fig 2.
TSSOP5
XSON6
XSON6
XSON6
XSON6
IEC logic symbol
Rev. 2 — 9 July 2010
1
2
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
plastic extremely thin small outline package; no leads;
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads;
6 terminals; body 1 × 1 × 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 × 1.0 × 0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0 × 1.0 × 0.35 mm
&
Marking code
p9
p9
p9
p9
p9
001aad599
4
Low-power 2-input AND gate with open-drain
[1]
Fig 3.
A
B
Logic diagram
74AUP1G09
© NXP B.V. 2010. All rights reserved.
Version
SOT353-1
SOT886
SOT891
SOT1115
SOT1202
001aad600
GND
Y
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