STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 154

• Manufacturer Part Number: STM32W108B-SK
• Description: STARTER KIT FOR STM32W108
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32W108B-SK

• Featured Product: STM32 Cortex-M3 Companion Products
• Contents: Board
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32W108xx
• Kit Contents: Board
• Features: IEEE
• Mfg Application Notes: STM32W108 Adjacent Channel Rejection Measurements
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General-purpose timers
10.3.15
10.3.16
154/209
31
15
31
15
30
14
30
14
Bits [1:0] TIM1_EXTRIGSEL
Timer 1 option register (TIM1_OR)
Address offset: 0xE050
Reset value:
Timer 2 option register (TIM2_OR)
Address offset: 0xF050
Reset value:
Bit 3 TIM_ORRSVD
Bit 2 TIM_CLKMSKEN
Bit 7 TIM_REMAPC4
Bit 6 TIM_REMAPC3
Bit 5 TIM_REMAPC2
Bit 4 TIM_REMAPC1
29
13
29
13
Reserved: this bit must always be set to 0.
Enables TIM1MSK when TIM1CLK is selected as the external trigger: 0 = TIM1MSK not used,
1 = TIM1CLK is ANDed with the TIM1MSK input.
Selects the external trigger used in external clock mode 2: 0 = PCLK, 1 = calibrated 1 kHz
clock, 2 = 32 kHz reference clock (if available), 3 = TIM1CLK pin.
Selects the GPIO used for TIM2_CH4: 0 = PA2, 1 = PB4.
Selects the GPIO used for TIM2_CH3: 0 = PA1, 1 = PB3.
Selects the GPIO used for TIM2_CH2: 0 = PA3, 1 = PB2.
Selects the GPIO used for TIM2_CH1: 0 = PA0, 1 = PB1.
28
12
28
12
Reserved
27
11
27
11
0x0000 0000
0x0000 0000
26
10
26
10
Reserved
25
25
9
9
Doc ID 16252 Rev 8
24
24
8
8
Reserved
Reserved
TIM_R
EMAP
C4
23
23
rw
7
7
TIM_R
EMAP
C3
22
22
rw
6
6
EMAPC
TIM_R
21
21
rw
5
5
2
STM32W108CB, STM32W108HB
TIM_R
EMAP
C1
20
20
rw
4
4
TIM_O
TIM_O
RRSV
RRSV
19
rw
19
rw
D
D
3
3
TIM_C
TIM_C
LKMS
LKMS
KEN
KEN
18
18
rw
rw
2
2
TIM1_EXTRIGS
TIM1_EXTRIGS
17
17
1
1
EL
EL
rw
rw
16
16
0
0