STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 43
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 43 of 209
- Download datasheet (3Mb)
STM32W108CB, STM32W108HB
6.4.3
6.4.4
31
15
31
15
30
14
30
14
Bits [15:0] WDOG_CTRL: Write 0xDEAD to disable or 0xEABE to enable.
Event timer
The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can
be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock.
FCLK is either the SCLK or PCLK as selected by CPU_CLK_SEL (see
switching on page
Slow timers (Watchdog and Sleeptimer) control and status registers
These registers are powered from the always-on power domain.
All registers are only writable when in System mode
Watchdog general control register (WDOG_CFG)
Register bits for general top level chip functions and protection.
Watchdog bits can only be written after first writing the appropriate code to the
WDOG_CTRL register.
Address:
Reset value:
Watchdog control register (WDOG_CTRL)
Requires magic number write to arm the watchdog enable or disable function.
Address:
Reset value:
Bit 1 WDOG_DIS: Watchdog disable
Bit 0 WDOG_EN: Watchdog enable
29
13
29
13
28
12
28
12
27
11
27
11
0x4000 6000
0x0000 0002
0x4000 6004
0x0000 0000
40).
26
10
26
10
25
25
9
9
Reserved
Doc ID 16252 Rev 8
24
24
WDOG_CTRL
8
8
Reserved
Reserved
w
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
Section 6.3.5: Clock
System modules
18
18
2
2
WDOG
_DIS
17
17
rw
1
1
43/209
WDOG
_EN
16
rw
16
0
0
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