STM32W108B-SK STMicroelectronics, STM32W108B-SK Datasheet - Page 47
STM32W108B-SK
Manufacturer Part Number
STM32W108B-SK
Description
STARTER KIT FOR STM32W108
Manufacturer
STMicroelectronics
Series
STM32r
Type
MCUr
Datasheets
1.STM32W108B-KEXT.pdf
(3 pages)
2.STM32W108B-KEXT.pdf
(209 pages)
3.STM32W108B-KEXT.pdf
(27 pages)
4.STM32W108B-KEXT.pdf
(6 pages)
5.STM32W108B-SK.pdf
(21 pages)
6.STM32W108B-KEXT.pdf
(14 pages)
7.STM32W108B-KEXT.pdf
(36 pages)
Specifications of STM32W108B-SK
Featured Product
STM32 Cortex-M3 Companion Products
Contents
Board
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
STM32
Silicon Family Name
STM32W108xx
Kit Contents
Board
Features
IEEE
Mfg Application Notes
STM32W108 Adjacent Channel Rejection Measurements
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- STM32W108B-KEXT PDF datasheet
- STM32W108B-KEXT PDF datasheet #2
- STM32W108B-KEXT PDF datasheet #3
- STM32W108B-KEXT PDF datasheet #4
- STM32W108B-SK PDF datasheet #5
- STM32W108B-KEXT PDF datasheet #6
- STM32W108B-KEXT PDF datasheet #7
- Current page: 47 of 209
- Download datasheet (3Mb)
STM32W108CB, STM32W108HB
31
15
31
15
30
14
30
14
Bits [15:0] SLEEPTMR_CMPBL_FIELD:
Sleep timer compare B low register (SLEEPTMR_CMPBL)
Address:
Reset value:
Sleep timer interrupt source register (INT_SLEEPTMRFLAG)
Address:
Reset value:
Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B
Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A
Bit 0 INT_SLEEPTMRWRAP: Sleep timer overflow
29
13
29
13
Note: Bits are cleared when set to ‘1’.
Note: Bits are cleared when set to ‘1’.
Note: Bits are cleared when set to ‘1’.
Sleep timer compare B low value [15:0].
Writing to this register puts value in hold register until a write to the SLEEPTMR_CMPBH
register.
Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’.
If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated.
Therefore it is recommended to disable interrupts before changing this register.
28
12
28
12
27
11
27
11
0x4000 A014
0x4000 6024
0x0000 FFFF
0x0000 0000
26
10
26
10
Reserved
25
25
9
9
r
Doc ID 16252 Rev 8
SLEEPTMR_CMPBL
24
24
8
8
Reserved
Reserved
rw
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
SLEEP
CMPB
INT_
TMR
System modules
18
18
rw
2
2
SLEEP
CMPA
INT_
TMR
17
17
rw
1
1
47/209
SLEEP
WRAP
INT_
TMR
16
16
rw
0
0
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