DP83815DVNG National Semiconductor, DP83815DVNG Datasheet - Page 31

• Manufacturer Part Number: DP83815DVNG
• Description: IC, ENET CTRL 10BASET, 100MBPS, LQFP-144
• Manufacturer: National Semiconductor

Specifications of DP83815DVNG

• Data Rate: 100Mbps
• Ethernet Type: 10BASE-T
• Supply Current: 170mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Subject to change without notice.
3.0 Functional Description
The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RXER, a receive data valid
flag RXDV, and a receive clock RXCLK for synchronous
transfer of the data. The receive clock can operate at 2.5
MHz to support 10 Mb/s operation modes or at 25 MHz to
support 100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TXEN, and a
transmit clock TXCLK which runs at 2.5 MHz or 25 MHz.
Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to indicate the reception of data from the network
or as a function of transmit data in Half Duplex mode. The
COL signal asserts as an indication of a collision which can
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.
3.12.6 Collision Detection
For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
active simultaneously. Collisions are reported by the COL
signal on the MII.
If the PHY is transmitting in 10 Mb/s mode when a collision
is detected, the collision is not reported until seven bits
MDC
MDIO
(STA)
Z
Idle
Z
0
Start
1
Opcode
(Write)
0
1
0
(PHYAD = 0Ch)
PHY Address
1 1 0 0 0 0 0 0 0
Figure 3-16 Typical MDC/MDIO Write Operation
(Continued)
Register Address
(00h = BMCR)
31
1
TA
have been received while in the collision state. This
prevents a collision being reported incorrectly due to noise
on the network. The COL signal remains set for the
duration of the collision.
If a collision occurs during a receive operation, it is
immediately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1µs after the transmission of
each packet, a Signal Quality Error (SQE) signal of
approximately 10 bit times is generated (internally) to
indicate successful transmission. SQE is reported as a
pulse on the COL signal of the MII.
3.12.7 Carrier Sense
Carrier Sense (CRS) is asserted due to receive activity,
once valid data is detected, during 10 Mb/s operation.
During 100 Mb/s operation CRS is asserted when a valid
link (SD) and two non-contiguous zeros are detected.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is de-asserted following an end of packet.
0 0 0
0 0
0 0 0
Register Data
0
0 0 0 0 0 0 0 0
Rev O
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Z
Idle
Z