DP83815DVNG National Semiconductor, DP83815DVNG Datasheet - Page 8

• Manufacturer Part Number: DP83815DVNG
• Description: IC, ENET CTRL 10BASET, 100MBPS, LQFP-144
• Manufacturer: National Semiconductor

Specifications of DP83815DVNG

• Data Rate: 100Mbps
• Ethernet Type: 10BASE-T
• Supply Current: 170mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.0 Pin Description
Media Independent Interface (MII)
Note: MII is normally tri-stated, unless enabled by CFG:EXT_PHY. See Section 4.2.2.
COL
CRS
MDC
MDIO
RXCLK
RXD3/MA9,
RXD2/MA8,
RXD1/MA7,
RXD0/MA6
RXDV/MA11
RXER/MA10
RXOE
TXCLK
TXD3/MA15,
TXD2/MA14,
TXD1/MA13,
TXD0/MA12
TXEN
Symbol
25, 24, 23, 22
12, 11, 10, 7
LQFP Pin
No(s)
28
29
15
14
13
31
30
5
4
6
(Continued)
A9, B9, D10,
B6, C6, A6,
LBGA Pin
No(s)
B10
A11
C11
D11
C5
B5
B8
D9
C9
A4
D7
D5
Dir
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Collision Detect: The COL signal is asserted high asynchronously
by the external PMD upon detection of a collision on the medium. It
will remain asserted as long as the collision condition persists.
Carrier Sense: This signal is asserted high asynchronously by the
external PMD upon detection of a non-idle medium.
Management Data Clock: Clock signal with a maximum rate of 2.5
MHz used to transfer management data for the external PMD on the
MDIO pin.
Management Data I/O: Bidirectional signal used to transfer
management information for the external PMD. (See Section 3.12.4
for details on connections when MII is used.)
Receive Clock: A continuous clock, sourced by an external PMD
device, that is recovered from the incoming data. During 100 Mb/s
operation RXCLK is 25 MHz and during 10 Mb/s this is 2.5 MHz.
Receive Data: Sourced from an external PMD, that contains data
aligned on nibble boundaries and are driven synchronous to RXCLK.
RXD[3] is the most significant bit and RXD[0] is the least significant
bit.
BIOS ROM Address: During external BIOS ROM access, these
signals become part of the ROM address.
Receive Data Valid: Indicates that the external PMD is presenting
recovered and decoded nibbles on the RXD signals, and that RXCLK
is synchronous to the recovered data in 100 Mb/s operation. This
signal will encompass the frame, starting with the Start-of-Frame
delimiter (JK) and excluding any End-of-Frame delimiter (TR).
BIOS ROM Address: During external BIOS ROM access, this signal
becomes part of the ROM address.
Receive Error: Asserted high synchronously by the external PMD
whenever it detects a media error and RXDV is asserted in 100 Mb/s
operation.
BIOS ROM Address: During external BIOS ROM access, this signal
becomes part of the ROM address.
Receive Output Enable: Used to disable an external PMD while the
BIOS ROM is being accessed.
Transmit Clock: A continuous clock that is sourced by the external
PMD. During 100 Mb/s operation this is 25 MHz +/- 100 ppm. During
10 Mb/s operation this clock is 2.5 MHz +/- 100 ppm.
Transmit Data: Signals which are driven synchronous to the TXCLK
for transmission to the external PMD. TXD[3] is the most significant
bit and TXD[0] is the least significant bit.
BIOS ROM Address: During external BIOS ROM access, these
signals become part of the ROM address.
Transmit Enable: This signal is synchronous to TXCLK and
provides precise framing for data carried on TXD[3-0] for the external
PMD. It is asserted when TXD[3-0] contains valid data to be
transmitted.
8
Description
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