DP83815DVNG National Semiconductor, DP83815DVNG Datasheet - Page 9

• Manufacturer Part Number: DP83815DVNG
• Description: IC, ENET CTRL 10BASET, 100MBPS, LQFP-144
• Manufacturer: National Semiconductor

Specifications of DP83815DVNG

• Data Rate: 100Mbps
• Ethernet Type: 10BASE-T
• Supply Current: 170mA
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.0 Pin Description
100BASE-TX/10BASE-T Interface
BIOS ROM/Flash Interface
Note: DP83815 supports NM27LV010 for the BIOS ROM interface device.
MCSN
MD7, MD6, MD5,
MD4/EEDO, MD3,
MD2,
MD1/CFGDISN,
MD0
MA5,
MA4/EECLK,
MA3/EEDI,
MA2/LED100LNK,
MA1/LED10LNK,
MA0/LEDACT
MWRN
MRDN
TPTDP, TPTDM
TPRDP,
TPRDM
Symbol
Symbol
LQFP Pin
141, 140, 139,
138, 135, 134,
3, 2, 1, 144,
54, 53
46, 45
No(s)
LQFP Pin
133, 132
143, 142
No(s)
129
131
130
(Continued)
LBGA Pin
D1, C1
G1, F1
No(s)
LBGA Pin
D13, D12,
D14, E11,
B11, A12,
B12, C13,
E14, F11,
C12, C14
F13, F12
No(s)
G13
F14
G11
A-O
Dir
A-I
Dir
I/O
O
O
O
O
Transmit Data: Differential common output driver. This differential
common output is configurable to either 10BASE-T or 100BASE-TX
signaling:
10BASE-T: Transmission of Manchester encoded 10BASE-T packet
data as well as Link Pulses (including Fast Link Pulses for Auto-
Negotiation purposes).
100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data.
The DP83815 will automatically configure this common output driver
for the proper signal type as a result of either forced configuration or
Auto-Negotiation.
Receive Data: Differential common input buffer. This differential
common input can be configured to accept either 100BASE-TX or
10BASE-T signaling:
10BASE-T: Reception of Manchester encoded 10BASE-T packet
data as well as normal Link Pulses and Fast Link Pulses for Auto-
Negotiation purposes.
100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3
data.
The DP83815 will automatically configure this common input buffer
to accept the proper signal type as a result of either forced
configuration or Auto-Negotiation.
9
BIOS ROM/Flash Chip Select: During a BIOS ROM/Flash
access, this signal is used to select the ROM device.
BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access
these signals are used to transfer data to or from the ROM/Flash
device.
MD[5:0] pins have internal weak pull ups.
MD6 and MD7 pins have internal weak pull downs.
BIOS ROM/Flash Address: During a BIOS ROM/Flash access,
these signals are used to drive the ROM/Flash address.
BIOS ROM/Flash Write: During a BIOS ROM/Flash access, this
signal is used to enable data to be written to the Flash device.
BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this
signal is used to enable data to be read from the Flash device.
Description
Description
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