SC16C754BIA68 NXP Semiconductors, SC16C754BIA68 Datasheet - Page 22

• Manufacturer Part Number: SC16C754BIA68
• Description: IC, UART, QUAD, 64BYTE FIFO, 16C754
• Manufacturer: NXP Semiconductors

Specifications of SC16C754BIA68

• No. Of Channels: 4
• Data Rate: 5Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Svhc: No SVHC (18-Jun-2010)
• Uart Features: DMA Signalling Capability, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 10.
[1]
[2]
[3]
[4]
SC16C754B_4
Product data sheet
A2 A1 A0 Register Bit 7
General register set
0
0
0
0
0
0
1
1
1
1
1
1
1
Special register set
0
0
Enhanced register set
0
1
1
1
1
These registers are accessible only when LCR[7] = 0.
This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
The Special register set is accessible only when LCR[7] is set to a logic 1.
Enhanced feature register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
SC16C754B internal registers
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
FIFO
Rdy
DLL
DLM
EFR
Xon1
Xon2
Xoff1
Xoff2
[3]
[1]
[4]
bit 7
bit 7
0/CTS
interrupt
enable
RX
trigger
level
(MSB)
FCR[0]
DLAB
1 or
1 / 4
clock
0/error in
RX FIFO
CD
bit 7
bit 7
bit 7
RX FIFO
D status
bit 7
bit 15
auto-CTS auto-RTS
bit 7
bit 7
bit 7
bit 7
Table 10
[2]
[2]
lists and describes the SC16C754B internal registers.
Bit 6
bit 6
bit 6
0/RTS
interrupt
enable
RX trigger
level (LSB)
FCR[0]
break
control bit
TCR and
TLR
enable
THR and
TSR empty
RI
bit 6
bit 6
bit 6
RX FIFO
C status
bit 6
bit 14
bit 6
bit 6
bit 6
bit 6
[2]
[2]
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Bit 5
bit 5
bit 5
0/Xoff
0/TX
trigger
level
(MSB)
0/CTS,
RTS
set parity
0/Xon Any
[2]
THR
empty
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
bit 5
bit 13
special
character
detect
bit 5
bit 5
bit 5
bit 5
Rev. 04 — 6 October 2008
[2]
[2]
Bit 4
bit 4
bit 4
0/X Sleep
mode
0/TX
trigger
level
(LSB)
0/Xoff
parity type
select
0/enable
loopback
break
interrupt
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
bit 4
bit 12
enable
enhanced
functions
[2]
bit 4
bit 4
bit 4
bit 4
[2]
[2]
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
interrupt
priority
bit 2
parity
enable
IRQ
enable
OP
framing
error
bit 3
bit 3
bit 3
TX FIFO
D status
bit 3
bit 11
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
CD
Bit 2
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
interrupt
priority
bit 1
number of
stop bits
FIFO
ready
enable
parity error overrun
bit 2
bit 2
bit 2
TX FIFO
C status
bit 2
bit 10
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
RI
Bit 1
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
interrupt
priority
bit 0
word
length
bit 1
RTS
error
bit 1
bit 1
bit 1
TX FIFO
B status
bit 1
bit 9
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
SC16C754B
DSR
© NXP B.V. 2008. All rights reserved.
Bit 0
bit 0
bit 0
RX data
available
interrupt
FIFO
enable
interrupt
status
word
length
bit 0
DTR
data in
receiver
bit 0
bit 0
bit 0
TX FIFO
A status
bit 0
bit 8
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
CTS
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Read/
Write
R
W
R/W
W
R
R/W
R/W
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W