SC16C754BIA68 NXP Semiconductors, SC16C754BIA68 Datasheet - Page 23

IC, UART, QUAD, 64BYTE FIFO, 16C754

SC16C754BIA68

Manufacturer Part Number
SC16C754BIA68
Description
IC, UART, QUAD, 64BYTE FIFO, 16C754
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C754BIA68

No. Of Channels
4
Data Rate
5Mbps
Supply Voltage Range
2.25V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
PLCC
No. Of Pins
68
Svhc
No SVHC (18-Jun-2010)
Uart Features
DMA Signalling Capability, Software Selectable Baud Rate Generator
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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NXP Semiconductors
SC16C754B_4
Product data sheet
7.1 Receiver Holding Register (RHR)
7.2 Transmit Holding Register (THR)
Remark: Refer to the notes under
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register (LCR). If the FIFO is disabled,
location zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 04 — 6 October 2008
Table 9
for more register access information.
SC16C754B
© NXP B.V. 2008. All rights reserved.
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