SC16C754BIA68 NXP Semiconductors, SC16C754BIA68 Datasheet - Page 25

• Manufacturer Part Number: SC16C754BIA68
• Description: IC, UART, QUAD, 64BYTE FIFO, 16C754
• Manufacturer: NXP Semiconductors

Specifications of SC16C754BIA68

• No. Of Channels: 4
• Data Rate: 5Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Svhc: No SVHC (18-Jun-2010)
• Uart Features: DMA Signalling Capability, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
SC16C754B_4
Product data sheet
7.4 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR.
shows the line control register bit settings.
Table 12.
Bit
7
6
5
4
3
2
1:0
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1:0]
Line control register bits description
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Description
Divisor latch enable.
Break control bit. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
Parity type select.
Parity enable.
Number of stop bits. Specifies the number of stop bits.
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received.
00 — 5 bits
01 — 6 bits
10 — 7 bits
11 — 8 bits
Rev. 04 — 6 October 2008
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for
the transmit and receive data
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for
the transmit and receive data
logic 0 = odd parity is generated (if LCR[3] = 1)
logic 1 = even parity is generated (if LCR[3] = 1)
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity
0 = 1 stop bit (word length = 5, 6, 7, 8)
1 = 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
SC16C754B
© NXP B.V. 2008. All rights reserved.
Table 12
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