DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 113

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• Receive Error Interrupts:
17.5
17.5.1
The CAN module has three transmit buffers. Each of
the three buffers occupies 14 bytes of data. Eight of the
bytes are the maximum 8 bytes of the transmitted
message. Five bytes hold the standard and extended
identifiers and other message arbitration information.
17.5.2
Transmit priority is a prioritization within each node of
the pending transmittable messages. There are
4 levels
(CiTXnCON<1:0>, where n = 0, 1 or 2 represents a
particular transmit buffer) for a particular message
buffer is set to ‘11’, that buffer has the highest priority.
If TXPRI<1:0> for a particular message buffer is set to
‘10’ or ‘01’, that buffer has an intermediate priority. If
TXPRI<1:0> for a particular message buffer is ‘00’, that
buffer has the lowest priority.
17.5.3
To initiate transmission of the message, the TXREQ bit
(CiTXnCON<3>) must be set. The CAN bus module
resolves any timing conflicts between setting of the
TXREQ bit and the Start-of-Frame (SOF), ensuring that if
the priority was changed, it is resolved correctly before the
SOF occurs. When TXREQ is set, the TXABT
(CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR
(CiTXnCON<4>) flag bits are automatically cleared.
© 2008 Microchip Technology Inc.
- Invalid Message Received:
- Receiver Overrun:
- Receiver Warning:
- Receiver Error Passive:
A receive error interrupt will be indicated by the
ERRIF bit. This bit shows that an error condition
occurred. The source of the error can be
determined by checking the bits in the CAN
Interrupt Status register, CiINTF.
If any type of error occurred during reception of
the last message, an error will be indicated by
the IVRIF bit.
The RXnOVR bit indicates that an overrun
condition occurred.
The RXWAR bit indicates that the receive error
counter (RERRCNT<7:0>) has reached the
warning limit of 96.
The RXEP bit indicates that the receive error
counter has exceeded the error passive limit of
127 and the module has gone into error passive
state.
Message Transmission
of
TRANSMIT BUFFERS
TRANSMIT MESSAGE PRIORITY
TRANSMISSION SEQUENCE
transmit
priority.
If
TXPRI<1:0>
Setting TXREQ bit simply flags a message buffer as
enqueued for transmission. When the module detects
an available bus, it begins transmitting the message
which has been determined to have the highest priority.
If the transmission completes successfully on the first
attempt, the TXREQ bit is cleared automatically, and an
interrupt is generated if TXIE was set.
If the message transmission fails, one of the error
condition flags will be set, and the TXREQ bit will
remain set indicating that the message is still pending
for transmission. If the message encountered an error
condition during the transmission attempt, the TXERR
bit will be set, and the error condition may cause an
interrupt. If the message loses arbitration during the
transmission attempt, the TXLARB bit is set. No
interrupt is generated to signal the loss of arbitration.
17.5.4
The system can also abort a message by clearing the
TXREQ bit associated with each message buffer.
Setting the ABAT bit (CiCTRL<12>) will request an
abort of all pending messages. If the message has not
yet started transmission, or if the message started but
is interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit and the TXnIF flag is not
automatically set.
17.5.5
The CAN module will detect the following transmission
errors:
• Acknowledge Error
• Form Error
• Bit Error
These transmission errors will not necessarily generate
an interrupt but are indicated by the transmission error
counter. However, each of these errors will cause the
transmission error counter to be incremented by one.
Once the value of the error counter exceeds the value
of 96, the ERRIF (CiINTF<5>) and the TXWAR bit
(CiINTF<10>) are set. Once the value of the error
counter exceeds the value of 96, an interrupt is
generated and the TXWAR bit in the Error Flag register
is set.
dsPIC30F5011/5013
ABORTING MESSAGE
TRANSMISSION
TRANSMISSION ERRORS
DS70116H-page 113