DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 134

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F5011/5013
FIGURE 19-3:
19.8
The analog input model of the 12-bit ADC is shown in
Figure 19-4. The total sampling time for the ADC is a
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source impedance (R
(R
FIGURE 19-4:
DS70116H-page 134
IC
Instruction Execution BSET ADCON1, ASAM
), and the internal sampling switch (R
ADCBUF0
ADCBUF1
ADCLK
ADC Acquisition Requirements
DONE
SAMP
Note: C
Legend: C
VA
PIN
HOLD
Rs
S
value depends on device package and is not tested. Effect of C
CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 T
SAMPLING TIME
12-BIT ADC ANALOG INPUT MODEL
), the interconnect impedance
V
I leakage
R
R
C
ANx
) must be allowed to fully
PIN
T
IC
SS
HOLD
C
PIN
= 1 T
T
SAMP
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
AD
various junctions
V
SS
DD
V
V
) imped-
T
T
= 0.6V
= 0.6V
= 14 T
T
CONV
AD
R
I leakage
± 500 nA
= 1 T
T
IC
SAMP
≤ 250Ω
AD
ance combine to directly affect the time required to
charge the capacitor C
of the analog sources must therefore be small enough
to fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage cur-
rents on the accuracy of the ADC, the maximum rec-
ommended source impedance, R
analog input channel is selected (changed), this sam-
pling function must be completed prior to starting the
conversion. The internal holding capacitor will be in a
discharged state prior to each sample operation.
Sampling
Switch
R
SS
= 14 T
PIN
T
CONV
R
negligible if Rs ≤ 2.5 kΩ.
SS
V
AD
SS
C
= DAC capacitance
= 18 pF
≤ 3 kΩ
HOLD
HOLD
© 2008 Microchip Technology Inc.
. The combined impedance
S
, is 2.5 kΩ. After the
AD