DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 217

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

T
Table Instruction Operation Summary ................................ 49
Temperature and Voltage Specifications
Timer1 Module .................................................................... 67
Timer2 and Timer3 Selection Mode .................................... 86
Timer2/3 Module ................................................................. 71
Timer4/5 Module ................................................................. 77
Timing Characteristics
Timing Diagrams
© 2008 Microchip Technology Inc.
Register Map............................................................. 153
AC ............................................................................. 176
16-bit Asynchronous Counter Mode ........................... 67
16-bit Synchronous Counter Mode ............................. 67
16-bit Timer Mode....................................................... 67
Gate Operation ........................................................... 68
Interrupt....................................................................... 68
Operation During Sleep Mode .................................... 68
Prescaler..................................................................... 68
Real-Time Clock ......................................................... 68
Register Map............................................................... 70
16-bit Timer Mode....................................................... 71
32-bit Synchronous Counter Mode ............................. 71
32-bit Timer Mode....................................................... 71
ADC Event Trigger...................................................... 74
Gate Operation ........................................................... 74
Interrupt....................................................................... 74
Operation During Sleep Mode .................................... 74
Register Map............................................................... 75
Timer Prescaler........................................................... 74
Register Map............................................................... 79
A/D Conversion
Bandgap Start-up Time............................................. 183
CAN Module I/O........................................................ 201
CLKOUT and I/O....................................................... 180
DCI Module
External Clock........................................................... 176
I
I
Input Capture (CAPX) ............................................... 186
OC/PWM Module ...................................................... 188
Oscillator Start-up Timer ........................................... 181
Output Compare Module........................................... 187
Power-up Timer ........................................................ 181
Reset......................................................................... 181
SPI Module
Type A, B and C Timer External Clock ..................... 184
Watchdog Timer........................................................ 181
CAN Bit ..................................................................... 114
Frame Sync, AC-Link Start of Frame........................ 122
Frame Sync, Multi-Channel Mode ............................ 122
I
PWM Output ............................................................... 87
2
2
2
C Bus Data
C Bus Start/Stop Bits
S Interface Frame Sync.......................................... 122
Interrupts............................................................. 69
Oscillator Operation ............................................ 69
Low-speed (ASAM = 0, SSRC = 000) .............. 204
AC-Link Mode ................................................... 191
Multichannel, I
Master Mode ..................................................... 197
Slave Mode ....................................................... 199
Master Mode ..................................................... 197
Slave Mode ....................................................... 199
Master Mode (CKE = 0) .................................... 192
Master Mode (CKE = 1) .................................... 193
Slave Mode (CKE = 0) ...................................... 194
Slave Mode (CKE = 1) ...................................... 195
2
S Modes ................................... 189
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
Timing Specifications
Trap Vectors ....................................................................... 40
U
UART Module
dsPIC30F5011/5013
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
DC Characteristics - Internal RC Accuracy .............. 178
A/D Conversion
Bandgap Start-up Time ............................................ 183
Brown-out Reset....................................................... 182
CAN Module I/O ....................................................... 201
CLKOUT and I/O ...................................................... 180
DCI Module
External Clock .......................................................... 177
I
I
Input Capture............................................................ 186
Oscillator Start-up Timer........................................... 182
Output Compare Module .......................................... 187
Power-up Timer ........................................................ 182
Reset ........................................................................ 182
Simple OC/PWM Mode ............................................ 188
SPI Module
Type A Timer External Clock.................................... 184
Type B Timer External Clock.................................... 185
Type C Timer External Clock.................................... 185
Watchdog Timer ....................................................... 182
PLL Clock ................................................................. 178
PLL Jitter .................................................................. 178
Address Detect Mode ............................................... 105
Auto Baud Support ................................................... 106
Baud Rate Generator ............................................... 105
Enabling and Setting Up........................................... 103
Framing Error (FERR) .............................................. 105
Idle Status................................................................. 105
Loopback Mode ........................................................ 105
Operation During CPU Sleep and Idle Modes.......... 106
Overview................................................................... 101
Parity Error (PERR) .................................................. 105
Receive Break .......................................................... 105
Receive Buffer (UxRXB)........................................... 104
Receive Buffer Overrun Error (OERR Bit) ................ 104
Receive Interrupt ...................................................... 104
Receiving Data ......................................................... 104
Receiving in 8-bit or 9-bit Data Mode ....................... 104
Reception Error Handling ......................................... 104
Transmit Break ......................................................... 104
Transmit Buffer (UxTXB) .......................................... 103
Transmit Interrupt ..................................................... 104
Transmitting Data ..................................................... 103
Transmitting in 8-bit Data Mode ............................... 103
2
2
C Bus Data (Master Mode) .................................... 198
C Bus Data (Slave Mode) ...................................... 200
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
Low-speed ........................................................ 205
AC-Link Mode................................................... 191
Multichannel, I
Master Mode (CKE = 0).................................... 192
Master Mode (CKE = 1).................................... 193
Slave Mode (CKE = 0)...................................... 194
Slave Mode (CKE = 1)...................................... 196
2
S Modes................................... 190
DD
) ......................................... 146
DD
DD
), Case 1 ..................... 146
), Case 2 ..................... 146
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