DSPIC30F5011-20I/PTG Microchip Technology, DSPIC30F5011-20I/PTG Datasheet - Page 69

• Manufacturer Part Number: DSPIC30F5011-20I/PTG
• Description: IC, DSC, 16BIT, 66KB, 40MHZ 5.5V TQFP-64
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-20I/PTG

• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5.1
When TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP
oscillator output signal, up to the value specified in the
Period register and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the CPU enters Sleep mode, the RTC will
continue to operate provided the 32 kHz external
crystal oscillator is active and the control bits have not
been changed. The TSIDL bit should be cleared to ‘0’
in order for RTC to continue operation in Idle mode.
© 2008 Microchip Technology Inc.
RTC OSCILLATOR OPERATION
9.5.2
When an interrupt event occurs, the respective interrupt
flag, T1IF, is asserted and an interrupt will be generated
if enabled. The T1IF bit must be cleared in software. The
respective Timer interrupt flag, T1IF, is located in the
IFS0 Status register in the interrupt controller.
Enabling an interrupt is accomplished via the
respective timer interrupt enable bit, T1IE. The timer
interrupt enable bit is located in the IEC0 Control
register in the interrupt controller.
dsPIC30F5011/5013
RTC INTERRUPTS
DS70116H-page 69