SST49LF008A-33-4C-WHE SILICON STORAGE TECHNOLOGY, SST49LF008A-33-4C-WHE Datasheet
SST49LF008A-33-4C-WHE
Specifications of SST49LF008A-33-4C-WHE
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SST49LF008A-33-4C-WHE Summary of contents
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... Mbit Firmware Hub SST49LF008A8 Mb Firmware Hub for Intel 8xx Chipsets FEATURES: • Firmware Hub for Intel 8xx Chipsets • 8 Mbit SuperFlash memory array for code/data storage – 1024K x8 • Flexible Erase Capability – Uniform 4 KByte Sectors – Uniform 64 KByte overlay blocks – ...
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... Mbit Firmware Hub To meet high density, surface mount requirements, the SST49LF008A devices are offered in a 32-lead TSOP package. In addition, the SST49LF008A is offered in 32- lead PLCC and 40-lead TSOP packages. See Figures 2, 3, and 4 for pin assignments and Table 1 for pin descriptions. ...
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... Mbit Firmware Hub SST49LF008A PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Byte-Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sector-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Characteristics (FWH Mode Characteristics (PP Mode PRODUCT ORDERING INFORMATION PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 © ...
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... FIGURE 1: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIGURE 2: Pin Assignments for 32-lead TSOP (8mm x 14mm FIGURE 3: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 4: Pin Assignments for 40-lead TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 5: Device Memory Map for SST49LF008A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FIGURE 6: Single-Byte Read Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FIGURE 7: Write Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIGURE 8: CLK Waveform FIGURE 9: Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIGURE 10: Output Timing Parameters ...
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... TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3: FWH Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 4: FWH Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 5: General Purpose Inputs Register TABLE 6: Block Locking Registers for SST49LF008A TABLE 7: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 8: Operation Modes Selection (PP Mode TABLE 9: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 10: DC Operating Characteristics (All Interfaces TABLE 11: Recommended System Power-up Timings ...
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... ID[3:0] FGPI[4:0] R/C# A[10:0] Programmer DQ[7:0] Interface OE# WE# FIGURE 1: Functional Block Diagram ©2006 Silicon Storage Technology, Inc. X-Decoder Address Buffers & Latches Control Logic IC RST Mbit Firmware Hub SST49LF008A SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 1161 B1.2 S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A PIN ASSIGNMENTS (IC) A10 (FGPI4) R/C# (CLK RST# (RST#) A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL Designates FWH Mode FIGURE 2: Pin Assignments for 32-lead TSOP (8mm x 14mm Designates FWH Mode FIGURE 3: Pin Assignments for 32-lead PLCC ©2006 Silicon Storage Technology, Inc. ...
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... FIGURE 4: Pin Assignments for 40-lead TSOP ©2006 Silicon Storage Technology, Inc Standard Pinout 9 10 Top View 11 12 Die Designates FWH Mode 8 8 Mbit Firmware Hub SST49LF008A (FWH4) WE# 37 (INIT#) OE# 36 (NC (RES) DQ7 34 (RES) DQ6 33 (RES) DQ5 32 (RES) DQ4 31 (NC (FWH3) DQ3 27 ...
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... Mbit Firmware Hub SST49LF008A TABLE 1: Pin Description Symbol Pin Name A -A Address -DQ Data 7 0 OE# Output Enable WE# Write Enable IC Interface Configuration Pin INIT# Initialize ID[3:0] Identification Inputs FGPI[4:0] General Purpose Inputs TBL# Top Block Lock FWH[3:0] FWH I/Os CLK Clock FWH4 FWH Input ...
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... Data Sheet DEVICE MEMORY MAP TBL# WP# for Block 0~14 FIGURE 5: Device Memory Map for SST49LF008A ©2006 Silicon Storage Technology, Inc. 0FFFFFH Block 15 Boot Block 0F0000H 0EFFFFH Block 14 0E0000H 0DFFFFH Block 13 0D0000H 0CFFFFH Block 12 0C0000H 0BFFFFH Block 11 0B0000H 0AFFFFH Block 10 0A0000H 09FFFFH ...
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... T2.7 1161 Firmware Hub Interface Cycles Addresses and data are transferred to and from the SST49LF008A by a series of “fields,” where each field con- tains 4 bits of data. SST49LF008A supports only single- byte Read and Write, and all fields are one clock cycle in length ...
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... YYYY is the most-significant nibble of the least-significant data byte. OUT In this clock cycle, the SST49LF008A has driven the bus to then Float all ones and then floats the bus prior to the next clock cycle. This is the first part of the bus “turnaround cycle.” ...
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... This is the first part of the bus “turnaround cycle.” Float then OUT The SST49LF008A takes control of the bus during this cycle. During the next clock cycle it will be driving the “sync” data. ...
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... Device Memory Hardware Write Protection The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF008A. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest flash memory address range for the SST49LF008A. ...
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... Multiple Device Selection The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID strapping in a system. When the SST49LF008A is used as a boot device, ID[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). The SST49LF008A will compare ...
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... Data Sheet TABLE 6: Block Locking Registers for SST49LF008A Register Block Size T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS10_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK 1. Default value at power up is 01H TABLE 7: Block Locking Register Bits Reserved Bit [7..2] Lock-Down Bit [1] ...
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... Reset RST# pin initiates a device reset. IL Read The Read operation of the SST49LF008A device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 13, for further details. Byte-Program Operation The SST49LF008A device is programmed on a byte-by- byte basis ...
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... If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling ( When the SST49LF008A device is in the internal Program operation, any attempt to read DQ plement of the true data. Once the Program operation is completed, DQ will produce true data. Note that even ...
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... Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of a six-byte load sequence. The SST49LF008A device is shipped with the Software Data Protection permanently enabled. See Table 9 for the specific software command codes ...
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... F0H -A can but no other value, for the Command sequence in PP Mode = Mbit Firmware Hub SST49LF008A 4th 5th 6th Write Cycle Write Cycle Data Addr Data Addr 3 Data 4 AAH 2AAAH 55H AAH ...
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... Mbit Firmware Hub SST49LF008A ELECTRICAL SPECIFICATIONS The AC and DC specifications for the FWH Interface signals (FWH[3:0], CLK, FWH4, and RST#) as defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 10 for the DC voltage and current specifications. Refer to the tables on pages 23 through 27 for the AC timing specifications for Clock, Read/Write, and Reset operations. ...
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... Min 0 +0 Max 0 =1500µ 0 =-500 µ min, LFRAME Mbit Firmware Hub SST49LF008A 1 and Address Input =V (PP mode FWH mode PP Mode TRC min Max DD DD and Address Input =V (PP mode FWH mode PP Mode TRC min , f=33 MHz, CE#=0 ≤ 0 and Address Input ...
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... Mbit Firmware Hub SST49LF008A TABLE 11: Recommended System Power-up Timings Symbol Parameter 1 T Power-up to Read Operation PU-READ 1 T Power-up to Write Operation PU-WRITE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter TABLE 12: Pin Impedance (V =3 ...
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... DD OUT Equation C - Equation D DD 26.7 V OUT -25+(V +1)/0.015 IN 25+(V -V -1)/0.015 =3.0-3.6V (FWH Mode) DD Min 1 100 100 Mbit Firmware Hub SST49LF008A Max Units µ 100 T15.3 1161 Units Test Conditions ≤ 0. < V OUT DD mA 0.3V < V < 0.9V DD OUT DD 1 0.7V < ...
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... Mbit Firmware Hub SST49LF008A V DD CLK RST#/INIT# FWH[3:0] FWH4 FIGURE 9: Reset Timing Diagram FWH [3:0] (Valid Output Data) FWH [3:0] (Float Output Data) FIGURE 10: Output Timing Parameters ©2006 Silicon Storage Technology, Inc. T PRST T KRST T RSTP T RSTF V TEST CLK T VAL T ON ...
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... Production testing may use different voltage values, but must correlate results back to these parameters. ©2006 Silicon Storage Technology, Inc. V TEST T SU Inputs Valid Value Units V/ns T18.3 1161 of overdrive over V and Mbit Firmware Hub SST49LF008A MAX 1161 F14.0 S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A AC Characteristics (PP Mode) TABLE 19: Read Cycle Timing Parameters, V Symbol Parameter T Read Cycle Time RC T RST# High to Row Address Setup RST T R/C# Address Set-up Time AS T R/C# Address Hold Time AH T Address Access Time AA T Output Enable Access Time ...
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... Silicon Storage Technology, Inc. T PRST T RSTP T RSTF T RC Row Address Column Address Row Address OLZ Data Valid 28 8 Mbit Firmware Hub SST49LF008A Row Address Sector-/Block-Erase T RSTE or Program operation aborted T RSTC Chip-Erase aborted T RST 1161 F15.0 Column Address OHZ High-Z 1161 F16.0 S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A T RSTP T RST RST# Addresses R/C# OE# WE# DQ 7-0 FIGURE 14: Write Cycle Timing Diagram (PP Mode) Row Addresses R/C# WE# OE FIGURE 15: Data# Polling Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. Row Address Column Address CWH T OES Data Valid Column ...
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... DQ 7 Byte-Program Address FIGURE 17: Byte-Program Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. T OET Four-Byte Code for Byte-Program 5555 2AAA 5555 WPH SB0 SB1 SB2 SB3 Data 30 8 Mbit Firmware Hub SST49LF008A D 1161 F19 Internal Program Starts 1161 F20.0 S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A Addresses 5555 R/C# OE WE# SB0 DQ 7 Sector Address FIGURE 18: Sector-Erase Timing Diagram (PP Mode) Addresses 5555 R/C# OE WE# SB0 DQ 7 Block Address FIGURE 19: Block-Erase Timing Diagram (PP Mode) ©2006 Silicon Storage Technology, Inc. Six-Byte code for Sector-Erase Operation 2AAA ...
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... Six-Byte code for Chip-Erase Operation 2AAA 5555 5555 2AAA WPH SB0 SB1 SB2 SB3 SB4 5555 0000 T IDA T WPH 55 90 SW1 SW2 Device ID = 5AH for SST49LF008A 32 8 Mbit Firmware Hub SST49LF008A 5555 T SCE Internal Erasure Starts SB5 10 1161 F23.0 0001 Device ID 1161 F24.2 S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A Three-Byte Sequence for Software ID Exit and Reset Addresses 5555 2AAA R/C# OE WE# SW0 DQ 7-0 AA FIGURE 22: Software ID Exit and Reset (PP Mode) V IHT INPUT V ILT AC test inputs are driven at V (0.9 IHT for inputs and outputs are V (0 FIGURE 23: AC Input/Output Reference Waveforms (PP Mode) ...
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... Silicon Storage Technology, Inc. Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program ( Data# Polling bit, or Toggle bit operation) Program Completed 1161 F28 Mbit Firmware Hub SST49LF008A S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A Internal Timer Byte- Program/Erase Initiated Wait SCE Program/Erase Completed FIGURE 26: Wait Options ©2006 Silicon Storage Technology, Inc. Toggle Bit Byte- Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase Completed 35 Data Sheet Data# Polling ...
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... Reset Command Sequence Write data: AAH Write data: F0H Address: 5555H Address: XXH Write data: 55H Wait T IDA Address: 2AAAH Write data: F0H Return to normal Address: 5555H operation Wait T IDA Return to normal operation 36 8 Mbit Firmware Hub SST49LF008A 1161 F30.0 S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A Chip-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Wait Options Chip erased ...
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... SST49LF00xA - XXX - XX Valid combinations for SST49LF008A SST49LF008A-33-4C-WHE SST49LF008A-33-4C-NHE SST49LF008A-33-4C-EIE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc. Suffix2 ...
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... Mbit Firmware Hub SST49LF008A PACKAGING DIAGRAMS TOP VIEW .495 .485 .453 Optional .447 Pin #1 .048 Identifier .042 .042 .048 .595 .553 .585 .547 .050 BSC Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). ...
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... FIGURE 30: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2006 Silicon Storage Technology, Inc. 8 Mbit Firmware Hub 1.05 0.95 0.50 BSC 8.10 0.27 7.90 0.17 0.15 0.05 DETAIL 1.20 max. 0.70 0.50 1mm 40 SST49LF008A 0˚- 5˚ 32-tsop-WH-7 S71161-11-000 3/06 ...
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... Mbit Firmware Hub SST49LF008A Pin # 1 Identifier 0.70 0.50 20.20 19.80 Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends, and 0.25 mm between leads. ...
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... Updated Data# Polling description • Corrected the values in Table 5 on page 15: General Purpose Inputs Register • Added note to Table 10 on page 22: DC Operating Characteristics 07 • Added 40-lead TSOP for SST49LF008A only • Corrected the • 2004 Data Book • Updated document status to Data Sheet 09 • ...