SST49LF008A-33-4C-WHE SILICON STORAGE TECHNOLOGY, SST49LF008A-33-4C-WHE Datasheet - Page 19

• Manufacturer Part Number: SST49LF008A-33-4C-WHE
• Description: MEMORY, FLASH, 8M, SERIAL, 32TSOP
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST49LF008A-33-4C-WHE

• Memory Size: 8Mbit
• Clock Frequency: 33MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Memory Type: Flash
• Memory Configuration: 1024K X 8
• Interface Type: Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 Mbit Firmware Hub
SST49LF008A
TABLE 8: Operation Modes Selection (PP Mode)
Data Protection
The SST49LF008A device provides both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit
the Write operation. This prevents inadvertent writes during
power-up or power-down.
©2006 Silicon Storage Technology, Inc.
Mode
Read
Program
Erase
Reset
Write Inhibit
Product Identification
DD
1. X can be V
2. Device ID = 5AH for SST49LF008A
Power Up/Down Detection: The Write operation is
IL
DD
or V
is less than 1.5V.
IH
, but no other value.
RST#
V
V
V
V
V
V
X
IH
IH
IH
IH
IH
IL
OE#
V
V
V
V
V
X
X
IH
IH
IL
IL
IL
WE#
V
V
V
V
V
X
X
19
IH
IH
IH
IL
IL
Software Data Protection (SDP)
SST49LF008A provides the JEDEC approved Software
Data Protection scheme for all data alteration operation,
i.e., Program and Erase. Any Program operation requires
the inclusion of a series of three-byte sequences. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
a six-byte load sequence. The SST49LF008A device is
shipped with the Software Data Protection permanently
enabled. See Table 9 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to Read mode, within T
DQ
D
D
X
High Z
High Z/D
High Z/D
Manufacturer’s ID (BFH)
Device ID
1
OUT
IN
OUT
OUT
2
Address
A
A
Sector or Block address,
XXH for Chip-Erase
X
X
X
A
A
IN
IN
18
18
-A
-A
1
1
=V
=V
S71161-11-000
IL
IL
, A
, A
0
0
=V
=
Data Sheet
V
IL
IH
RC.
T8.6 1161
3/06