SST49LF008A-33-4C-WHE SILICON STORAGE TECHNOLOGY, SST49LF008A-33-4C-WHE Datasheet - Page 9

• Manufacturer Part Number: SST49LF008A-33-4C-WHE
• Description: MEMORY, FLASH, 8M, SERIAL, 32TSOP
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST49LF008A-33-4C-WHE

• Memory Size: 8Mbit
• Clock Frequency: 33MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Memory Type: Flash
• Memory Configuration: 1024K X 8
• Interface Type: Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 Mbit Firmware Hub
SST49LF008A
TABLE 1: Pin Description
©2006 Silicon Storage Technology, Inc.
Symbol
A
DQ
OE#
WE#
IC
INIT#
ID[3:0]
FGPI[4:0] General Purpose Inputs
TBL#
FWH[3:0] FWH I/Os
CLK
FWH4
RST#
WP#
R/C#
RES
V
V
NC
10
DD
SS
1. I = Input, O = Output
-A
7
-DQ
0
0
Pin Name
Address
Data
Output Enable
Write Enable
Interface
Configuration Pin
Initialize
Identification Inputs
Top Block Lock
Clock
FWH Input
Reset
Write Protect
Row/Column Select
Reserved
Power Supply
Ground
No Connection
Type
PWR
PWR
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
PP FWH
Interface
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Functions
Inputs for low-order addresses during Read and Write operations.
Addresses are internally latched during a Write cycle. For the pro-
gramming interface, these addresses are latched by R/C# and share
the same pins as the high-order address inputs.
To output data during Read cycles and receive input data during
Write cycles. Data is internally latched during a Write cycle. The out-
puts are in tri-state when OE# is high.
To gate the data output buffers
To control the Write operations
This pin determines which interface is operational. When held high,
programmer mode is enabled and when held low, FWH mode is
enabled. This pin must be setup at power-up or before return from
reset and not change during device operation. This pin is internally
pulled- down with a resistor between 20-100 KΩ.
This is the second reset pin for in-system use. This pin is internally
combined with the RST# pin; If this pin or RST# pin is driven low,
identical operation is exhibited.
These four pins are part of the mechanism that allows multiple parts
to be attached to the same bus. The strapping of these pins is used
to identify the component.The boot device must have ID[3:0]=0000
and it is recommended that all subsequent devices should use
sequential up-count strapping. These pins are internally pulled-down
with a resistor between 20-100 KΩ.
These individual inputs can be used for additional board flexibility.
The state of these pins can be read through GPI_REG register.
These inputs should be at their desired state before the start of the
PCI clock cycle during which the read is attempted, and should
remain in place until the end of the Read cycle. Unused GPI pins
must not be floated.
When low, prevents programming to the Boot Block sectors at top of
memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
I/O Communications
To provide a clock input to the control unit
Input Communications
To reset the operation of the device
When low, prevents programming to all but the highest addressable
blocks. When WP# is high it disables hardware write protection for
these blocks. This pin cannot be left unconnected.
Select For the Programming interface, this pin determines whether
the address pins are pointing to the row addresses, or to the column
addresses.
These pins must be left unconnected.
To provide power supply (3.0-3.6V)
Circuit ground (OV reference) All V
Unconnected pins
9
SS
pins must be grounded.
S71161-11-000
Data Sheet
T1.4 1161
3/06