SST49LF008A-33-4C-WHE SILICON STORAGE TECHNOLOGY, SST49LF008A-33-4C-WHE Datasheet - Page 12

• Manufacturer Part Number: SST49LF008A-33-4C-WHE
• Description: MEMORY, FLASH, 8M, SERIAL, 32TSOP
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST49LF008A-33-4C-WHE

• Memory Size: 8Mbit
• Clock Frequency: 33MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Memory Type: Flash
• Memory Configuration: 1024K X 8
• Interface Type: Parallel
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
TABLE 3: FWH Read Cycle
©2006 Silicon Storage Technology, Inc.
FIGURE 6: Single-Byte Read Waveforms
1. Field contents are valid on the rising edge of the present clock cycle.
Clock
Cycle
3-9
10
11
12
13
14
15
16
17
1
2
FWH[3:0]
FWH4
CLK
IMADDR
RSYNC
IMSIZE
START
IDSEL
Name
TAR0
TAR1
TAR0
TAR1
Field
DATA
DATA
STR
IDS
Field Contents
0000 (READY)
0000 (1 byte)
0000 to 1111
1111 (float)
1111 (float)
FWH[3:0]
YYYY
YYYY
YYYY
1101
1111
1111
1
IMADDR
FWH[3:0]
then Float
then Float
Float then
Direction
then OUT
Float
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
12
These seven clock cycles make up the 28-bit memory
Comments
FWH4 must be active (low) for the part to respond. Only the
last start field (before FWH4 transitions high) should be rec-
ognized. The START field contents indicate a FWH memory
Read cycle.
Indicates which FWH device should respond. If the to IDSEL (ID
select) field matches the value ID[3:0], then that particular device
will respond to the whole bus cycle.
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
A field of this size indicates how many bytes will be or trans-
ferred during multi-byte operations. The SST49LF008A will
only support single-byte operation. IMSIZE=0000b
In this clock cycle, the master (Intel ICH) has driven the bus
then float to all ‘1’s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.”
The SST49LF008A takes control of the bus during this cycle.
During the next clock cycle, it will be driving “sync data.”
During this clock cycle, the FWH will generate a “ready-
sync” (RSYNC) indicating that the least-significant nibble of
the least-significant byte will be available during the next
clock cycle.
YYYY is the least-significant nibble of the least-significant
data byte.
YYYY is the most-significant nibble of the least-significant
data byte.
In this clock cycle, the SST49LF008A has driven the bus to
all ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
The master (Intel ICH) resumes control of the bus during
this cycle.
IMS
TAR
RSYNC
8 Mbit Firmware Hub
DATA
SST49LF008A
1161 F09.0
S71161-11-000
TAR
T3.3 1161
3/06