LPC1113FHN33/301 NXP Semiconductors, LPC1113FHN33/301 Datasheet - Page 28

• Manufacturer Part Number: LPC1113FHN33/301
• Description: MCU, 32BIT, 24KFLASH, CORTEX-M0, 33HVQFN
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/301

• Controller Family/series: ARM Cortex-M0
• No. Of I/o's: 28
• Ram Memory Size: 8KB
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Core Size: 32bit
• Program Memory Size: 24KB
• Oscillator Type: External, Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1111_12_13_14
Product data sheet
7.15.5.1 Power profiles (LPC1100L series, LPC111x/102/202/302 only)
7.15.5.2 Sleep mode
7.15.5.3 Deep-sleep mode
7.15.5.4 Deep power-down mode
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC1111/12/13/14 for one of the following power modes:
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the watchdog oscillator and the
BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows
for additional power savings.
Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip
from Deep-sleep mode.
Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source
should be switched to IRC before entering Deep-sleep mode, because the IRC can be
switched on and off glitch-free.
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC1111/12/13/14 can wake up from Deep power-down mode via the
WAKEUP pin.
A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
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Default mode corresponding to power configuration after reset.
CPU performance mode corresponding to optimized processing capability.
Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 February 2011
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
© NXP B.V. 2011. All rights reserved.
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